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DOCUMENT NUMBER 9S12C-FamilyDGV1/D
MC9S12C Family Device User Guide V01.01
Original Release Date: 25 JAN 2003 Revised: 12 AUGUST 2003
Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c)Motorola, Inc., 2002
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
Revision History
Version Revision Effective Number Date Date
00.01 00.02 00.03 25.JAN.03 25.JAN.03 07.FEB.03 07.FEB.03 25.FEB.03 25.FEB.03
Author
Description of Changes
Original Version. Based on C32 user guide version 01.12 Enhanced PortK description Part number table revision in preface QFP112 Emulation pinout correction Enhanced part number explanation in preface Reduced pseudo STOP current spec. for C64,C96,C128 Enhanced PortAD signal description Corrected VDDR description in 2.4.2 Revised pin leakage in electrical parameters SPI timing parameter table correction Output drive high value reduced in 3V range PE[4:2] Pull-Up spec out of reset changed 3V Expansion bus timing parameters not tested in production Minimum bus frequency specification increased to 0.25MHz. Parameter classification added to Appendix Table C-2. IOH changed to 4mA for 3V range. LVR level defined.for C32. Run IDD changed for C32. Block guide reference table updated Added PCB layout guide for Pierce oscillator configuration IOL parameter updated in 3.3V range Updated PARTID listing due to C128 ECO revision
00.04
15.APR.03 15.APR03
00.05
05.MAY.03 05.MAY.03
00.06
21.MAY.03 21.MAY.03
01.00 01.01
15.JUL.03
15.JUL03
12.AUG.03 12.AUG.03
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
Table of Contents
Section 1 Introduction
1.1 1.2 1.3 1.4 1.5 1.6 1.7 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Section 2 Signal Description
2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.2.1 Pin Initialization for 48 & 52 Pin LQFP bond-out versions . . . . . . . . . . . . . . . . . . 50 2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.3.1 EXTAL, XTAL -- Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.3.2 RESET -- External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.3.3 TEST / VPP -- Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.3.4 XFC -- PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.3.5 BKGD / TAGHI / MODC -- Background Debug, Tag High & Mode Pin . . . . . . . 52 2.3.6 PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins . . . . . . . . . . . . . . . . . . . . 52 2.3.7 PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 52 2.3.8 PE7 / NOACC / XCLKS -- Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.3.9 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.3.10 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.3.11 PE4 / ECLK-- Port E I/O Pin [4] / E-Clock Output . . . . . . . . . . . . . . . . . . . . . . . . 54 2.3.12 PE3 / LSTRB -- Port E I/O Pin [3] / Low-Byte Strobe (LSTRB). . . . . . . . . . . . . . 55 2.3.13 PE2 / R/W -- Port E I/O Pin [2] / Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.3.14 PE1 / IRQ -- Port E input Pin [1] / Maskable Interrupt Pin . . . . . . . . . . . . . . . . . 55 2.3.15 PE0 / XIRQ -- Port E input Pin [0] / Non Maskable Interrupt Pin . . . . . . . . . . . . 55 2.3.16 PAD[7:0] / AN[7:0] -- Port AD I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.3.17 PP[7] / KWP[7] -- Port P I/O Pin [7]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.18 PP[6] / KWP[6]/ROMCTL -- Port P I/O Pin [6] . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.19 PP[5:0] / KWP[5:0] / PW[5:0] -- Port P I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . 56
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2.3.20 PJ[7:6] / KWJ[7:6] -- Port J I/O Pins [7:6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.21 PM5 / SCK -- Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.22 PM4 / MOSI -- Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.23 PM3 / SS -- Port M I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.24 PM2 / MISO -- Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.25 PM1 / TXCAN -- Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.26 PM0 / RXCAN -- Port M I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.27 PS[3:2] -- Port S I/O Pins [3:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.28 PS1 / TXD -- Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.29 PS0 / RXD -- Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.30 PPT[7:5] / IOC[7:5] -- Port T I/O Pins [7:5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.31 PT[4:0] / IOC[4:0] / PW[4:0]-- Port T I/O Pins [4:0] . . . . . . . . . . . . . . . . . . . . . . . 57 2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.4.1 VDDX,VSSX -- Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . 57 2.4.2 VDDR, VSSR -- Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator 58 2.4.3 VDD1, VDD2, VSS1, VSS2 -- Internal Logic Power Pins . . . . . . . . . . . . . . . . . . 58 2.4.4 VDDA, VSSA -- Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 58 2.4.5 VRH, VRL -- ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 58 2.4.6 VDDPLL, VSSPLL -- Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . 58
Section 3 System Clock Description Section 4 Modes of Operation
4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Section 5 Resets and Interrupts
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5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3.1 Reset Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3.2 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Section 6 HCS12 Core Block Description
6.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.1.1 PPAGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.1.2 BDM alternate clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.1.3 Extended Address Range Emulation Implications . . . . . . . . . . . . . . . . . . . . . . . . 66
Section 7 Voltage Regulator (VREG) Block Description
7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.1.1 VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.1.2 VDD1, VDD2, VSS1, VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Section 8 Recommended Printed Circuit Board Layout Section 9 Clock Reset Generator (CRG) Block Description
9.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.1.1 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Section 10 Oscillator (OSC) Block Description Section 11 Timer (TIM) Block Description Section 12 Analog to Digital Converter (ATD) Block Description
12.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.1.1 VRL (voltage reference low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Section 13 Serial Communications Interface (SCI) Block Description Section 14 Serial Peripheral Interface (SPI) Block Description Section 15 Flash Block Description
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Section 16 RAM Block Description Section 17 Pulse Width Modulator (PWM) Block Description Section 18 MSCAN Block Description Section 19 Port Integration Module (PIM) Block Description Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 83 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Appendix B Electrical Specifications
B.1 B.2 B.3 B.3.1 B.3.2 B.4 B.4.1 B.4.2 B.4.3 B.4.4 B.4.5 B.5 B.5.1 B.5.2 Voltage Regulator Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Chip Power-up and LVI/LVR graphical explanation . . . . . . . . . . . . . . . . . . . . . . . . . 92 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ATD Operating Characteristics In 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ATD Operating Characteristics In 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Factors influencing accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ATD accuracy (5V Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 ATD accuracy (3.3V Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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B.6 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 B.6.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 B.6.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 B.6.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 B.7 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 B.8 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Appendix C Electrical Specifications
C.1 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 C.2 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 C.3 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 C.3.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Appendix D Package Information
D.1 D.2 D.3 D.4 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 52-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 48-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Appendix E Emulation Information
E.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 E.1.1 PK[2:0] / XADDR[16:14]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 E.2 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
List of Figures
Figure 0-1 Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 1-5 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 3-1 Figure 8-1 Figure 8-2 Figure 8-3 Figure 8-4 Figure 8-5 Figure 8-6 Figure B-1 Figure B-2 Figure B-3 Figure B-4 Figure B-5 Figure C-1 Figure C-2 Figure C-3 Figure C-4 Figure C-5 Figure D-1 Figure D-2 Figure D-3 Order Partnumber Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MC9S12C-Family Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MC9S12C128 User configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . . 25 MC9S12C96 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . . 26 MC9S12C64 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . . 27 MC9S12C32 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . . 28 Pin Assignments in 80 QFP for MC9S12C-Family . . . . . . . . . . . . . . . . . . . . 46 Pin assignments in 52 LQFP for MC9S12C-Family. . . . . . . . . . . . . . . . . . . . 47 Pin Assignments in 48 LQFP for MC9S12C-Family . . . . . . . . . . . . . . . . . . . 48 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Recommended PCB Layout (48 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Recommended PCB Layout (52 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Recommended PCB Layout (80 QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Recommended PCB Layout for 48 LQFP Pierce Oscillator . . . . . . . . . . . . . 72 Recommended PCB Layout for 52 LQFP Pierce Oscillator . . . . . . . . . . . . . 73 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . 74 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) . . . . . 92 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . 110 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . 124 52-pin LQFP Mechanical Dimensions (case no. 848D-03) . . . . . . . . . . . . 125 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F) . . . . . . 126
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
Figure 19-1 Pin Assignments in 112-pin LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanical Dimensions (case no. 841B)129
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
List of Tables
Table 0-1 Package Option Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 0-2 Part Number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 0-3 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 1-1 Device Register Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 $0000 - $000FMEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) 29 $0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control) 29 $0018 - $0018 Miscellaneous Peripherals (Device User Guide) 30 $0019 - $0019 VREG3V3 (Voltage Regulator) 30 $0015 - $0016 INT map 1 of 2 (HCS12 Interrupt) 30 $0017 - $0017MMC map 2 of 4 (HCS12 Module Mapping Control) 30 $001A - $001B Miscellaneous Peripherals (Device User Guide) 30 $001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, 31 Device User Guide) 31 $001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) 31 $001F - $001F INT map 2 of 2 (HCS12 Interrupt) 31 $0020 - $002F DBG (including BKP) map 1 of 1 (HCS12 Debug ) 31 $0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control) 32 $0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) 32 $0034 - $003F CRG (Clock and Reset Generator) 32 $0040 - $006F TIM (Timer 16 Bit 8 Channels) 33 $0070 - $007F Reserved 35 $0080 - $009F ATD (Analog to Digital Converter 10 Bit 8 Channel) 35 $00A0 - $00C7 Reserved 36 $00D0 - $00D7 Reserved 37 $00C8 - $00CF SCI (Asynchronous Serial Interface) 37 $00D8 - $00DF SPI (Serial Peripheral Interface) 37 $00E0 - $00FF PWM (Pulse Width Modulator) 38 $0100 - $010F Flash Control Register 39 $0110 - $013F Reserved 40 $0140 - $017F CAN (Motorola Scalable CAN - MSCAN) 40 Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . 41 $0180 - $023F Reserved 42 $0240 - $027F PIM (Port Interface Module) 42
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$0280 - $03FF Reserved space 45 Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 2-2 MC9S12C-Family Power and Ground Connection Summary . . . . . . . . . . . . . 58 Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 5-2 Reset Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 6-1 Device Specfic Flash PAGE Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 8-1 Recommended External Component Values. . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table A-3 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table A-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table A-7 3.3V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table A-8 Supply Current Characteristics for MC9S12C32 . . . . . . . . . . . . . . . . . . . . . . . 89 Table A-9 Supply Current Characteristics for MC9S12C64,MC9S12C96,MC9S12C128 90 Table B-1 Voltage Regulator Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table B-2 Voltage Regulator - Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table B-3 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table B-4 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table B-5 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table B-6 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table B-7 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table B-8 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table B-9 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table B-10 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table B-11 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table B-12 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table B-13 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table C-1 Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table C-2 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table C-3 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
Table C-4 Table C-5
Expanded Bus Timing Characteristics (5V Range). . . . . . . . . . . . . . . . . . . . 120 Expanded Bus Timing Characteristics (3.3V Range) . . . . . . . . . . . . . . . . . . 121
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
Preface
The Device User Guide provides information about the MC9S12C-Family devices made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes the HCS12 Core User Guide and all the individual Block User Guides of the implemented modules. In an effort to reduce redundancy all module specific information is located only in the respective Block User Guide. If applicable, special implementation details of the module are given in the block description sections of this document. The C Family offers an extensivce range of package temperature and speed options. Table 0-1 summarises the package option and size configuration. Table 0-2 lists the partnumber coding based on the package, speed and temperature and preliminary die options Table 0-1 Package Option Summary
Package
48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP
Device
MC9S12C128 MC9S12C128 MC9S12C128 MC9S12C96 MC9S12C96 MC9S12C96 MC9S12C64 MC9S12C64 MC9S12C64 MC9S12C32 MC9S12C32 MC9S12C32
Part Number
MC9S12C128 MC9S12C128 MC9S12C128 MC9S12C96 MC9S12C96 MC9S12C96 MC9S12C64 MC9S12C64 MC9S12C64 MC9S12C32 MC9S12C32 MC9S12C32
Mask1 set
0L09S 0L09S 0L09S TBD TBD TBD TBD TBD TBD 1L45J 1L45J 1L45J
Temp.2 Option s
M, V, C M, V, C M, V, C M, V, C M, V, C M, V, C M, V, C M, V, C M, V, C M, V, C M, V, C M, V, C
Flash
RAM
I/O3,4
31
128K
4K
35 60 31
96K
4K
35 60 31
64K
4K
35 60 31
32K
2K
35 60
NOTES: 1. Maskset dependent errata can be accessed at http://e-www.motorola.com/wbapp/sps/site/prod_summary.jsp 2. C: TA = 85C, f = 25MHz. V: TA=105C, f = 25MHz. M: TA= 125C, f = 25MHz 3. All derivatives feature 1 CAN, 1 SCI, 1 SPI, an 8-channel A/D, a 6-channel PWM and an 8 channel timer. 4. I/O is the sum of ports capable to act as digital input or output.
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
MC9S12 C32 (P)C FU
25
Speed Option Package Option Temperature Option Preliminary Option Device Title Controller Family
Temperature Options C = -40C to 85C V = -40C to 105C M = -40C to 125C Package Options FU = 80QFP PB = 52LQFP FA = 48LQFP Speed Options 25 = 25MHz bus 16 = 16MHz bus
Figure 0-1 Order Partnumber Coding Table 0-2 Part Number Coding
Part Number
MC9S12C64PCFA16 MC9S12C64PCPB16 MC9S12C64PCFU16 MC9S12C64CFA16 MC9S12C64CPB16 MC9S12C64CFU16 MC9S12C64PVFA16 MC9S12C64PVPB16 MC9S12C64PVFU16 MC9S12C64VFA16 MC9S12C64VPB16 MC9S12C64VFU16 MC9S12C64PMFA16 MC9S12C64PMPB16 MC9S12C64PMFU16 MC9S12C64MFA16 MC9S12C64MPB16 MC9S12C64MFU16 MC9S12C64PCFA25 MC9S12C64PCPB25 MC9S12C64PCFU25 MC9S12C64CFA25 MC9S12C64CPB25 MC9S12C64CFU25 MC9S12C64PVFA25 MC9S12C64PVPB25 MC9S12C64PVFU25 MC9S12C64VFA25
Mask set
0L09S 0L09S 0L09S TBD TBD TBD 0L09S 0L09S 0L09S TBD TBD TBD 0L09S 0L09S 0L09S TBD TBD TBD 0L09S 0L09S 0L09S TBD TBD TBD 0L09S 0L09S 0L09S TBD
Temp.
-40C, 85C -40C, 85C -40C, 85C -40C, 85C -40C, 85C -40C, 85C -40C, 105C -40C, 105C -40C, 105C -40C,105C -40C,105C -40C, 105C -40C, 125C -40C, 125C -40C, 125C -40C,125C -40C,125C -40C, 125C -40C, 85C -40C, 85C -40C, 85C -40C, 85C -40C, 85C -40C, 85C -40C, 105C -40C, 105C -40C, 105C -40C,105C
Package
48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP
Speed
16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz
Description
PreliminaryC64 using C128 die PreliminaryC64 using C128 die PreliminaryC64 using C128 die Final C64 using C64 die Final C64 using C64 die Final C64 using C64 die PreliminaryC64 using C128 die PreliminaryC64 using C128 die PreliminaryC64 using C128 die Final C64 using C64 die Final C64 using C64 die Final C64 using C64 die PreliminaryC64 using C128 die PreliminaryC64 using C128 die PreliminaryC64 using C128 die Final C64 using C64 die Final C64 using C64 die Final C64 using C64 die PreliminaryC64 using C128 die PreliminaryC64 using C128 die PreliminaryC64 using C128 die Final C64 using C64 die Final C64 using C64 die Final C64 using C64 die PreliminaryC64 using C128 die PreliminaryC64 using C128 die PreliminaryC64 using C128 die Final C64 using C64 die
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01 Mask set
TBD TBD 0L09S 0L09S 0L09S TBD TBD TBD 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Part Number
MC9S12C64VPB25 MC9S12C64VFU25 MC9S12C64PMFA25 MC9S12C64PMPB25 MC9S12C64PMFU25 MC9S12C64MFA25 MC9S12C64MPB25 MC9S12C64MFU25 MC9S12C32CFA16 MC9S12C32CPB16 MC9S12C32CFU16 MC9S12C32VFA16 MC9S12C32VPB16 MC9S12C32VFU16 MC9S12C32MFA16 MC9S12C32MPB16 MC9S12C32MFU16 MC9S12C32CFA25 MC9S12C32CPB25 MC9S12C32CFU25 MC9S12C32VFA25 MC9S12C32VPB25 MC9S12C32VFU25 MC9S12C32MFA25 MC9S12C32MPB25 MC9S12C32MFU25 MC9S12C128CFA16 MC9S12C128CPB16 MC9S12C128CFU16 MC9S12C128VFA16 MC9S12C128VPB16 MC9S12C128VFU16 MC9S12C128MFA16 MC9S12C128MPB16 MC9S12C128MFU16 MC9S12C128CFA25 MC9S12C128CPB25 MC9S12C128CFU25 MC9S12C128VFA25 MC9S12C128VPB25 MC9S12C128VFU25 MC9S12C128MFA25 MC9S12C128MPB25 MC9S12C128MFU25
Temp.
-40C,105C -40C, 105C -40C, 125C -40C, 125C -40C, 125C -40C,125C -40C,125C -40C, 125C -40C, 85C -40C, 85C -40C, 85C -40C,105C -40C,105C -40C, 105C -40C,125C -40C,125C -40C, 125C -40C, 85C -40C, 85C -40C, 85C -40C,105C -40C,105C -40C, 105C -40C,125C -40C,125C -40C, 125C -40C, 85C -40C, 85C -40C, 85C -40C,105C -40C,105C -40C, 105C -40C,125C -40C,125C -40C, 125C -40C, 85C -40C, 85C -40C, 85C -40C,105C -40C,105C -40C, 105C -40C,125C -40C,125C -40C, 125C
Package
52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP
Speed
25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz
Description
Final C64 using C64 die Final C64 using C64 die PreliminaryC64 using C128 die PreliminaryC64 using C128 die PreliminaryC64 using C128 die Final C64 using C64 die Final C64 using C64 die Final C64 using C64 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
Table 0-3 Document References
User Guide 1
CPU12 Reference Manual HCS12 Debug (DBG) Block Guide HCS12 Background Debug (BDM) Block Guide HCS12 Module Mapping Control (MMC) Block Guide HCS12 Multiplexed External Bus Interface (MEBI) Block Guide HCS12 Interrupt (INT) Block Guide Analog To Digital Converter: 10 Bit 8 Channel (ATD_10B8C) Block Guide Clock and Reset Generator (CRG) Block Guide Serial Communications Interface (SCI) Block Guide Serial Peripheral Interface (SPI) Block Guide Motorola Scalable CAN (MSCAN) Block Guide Pulse Width Modulator: 8 bit, 6 channel (PWM_8B6C) Block Guide Timer : 16 bit, 8 channel (TIM_16B8C) Block Guide Voltage Regulator (VREG) Block Guide Oscillator (OSC) Block Guide (Port Integration Module) PIM_9C32 Block Guide 32Kbyte Flash EEPROM (FTS32K) Block Guide 64Kbyte Flash EEPROM (FTS64K) Block Guide 128Kbyte Flash EEPROM (FTS128K) Block Guide
Version
V04 V01 V04 V04 V03 V01 V02 V04 V02 V03 V02 V01 V01 V02 V02 V01 V01 V01 V01
Document Order Number
CPU12RM/AD S12DBGV1/D S12BDMV4/D S12MMCV4/D S12MEBIV3/D S12INTV1/D S12ATD10B8CV2/D S12CRGV4/D S12SCIV2/D S12SPIV3/D S12MSCANV2/D S12PWM8B6V1/D S12TIM16B8CV1/D S12VREG3V3V2/D S12OSCV2/D S12C32PIMV1/D S12FTS32KV1/D S12FTS64KV1/D S12FTS128KV1/D
NOTES: 1. For the C32 refer to the 32K flash, for the C64 the 64K flash, for the C96 the 96K flash and C128 the 128K flash document
Terminology
Acronyms and Abbreviations New or invented terms, symbols, and notations
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
Section 1 Introduction
1.1 Overview
The MC9S12C-Family is a 48/52/80 pin Flash-based Industrial/Automotive network control MCU family.. Members of the MC9S12C-Family deliver the power and flexibility of our 16 Bit core (CPU12) family to a whole new range of cost and space sensitive, general purpose Industrial and Automotive network applications. All MC9S12C-Family members are comprised of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 128K bytes of Flash EEPROM, up to 4K bytes of RAM, an asynchronous serial communications interface (SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer module (TIM), a 6-channel 8-bit Pulse Width Modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC) and a CAN 2.0 A, B software compatible module (MSCAN12). The MC9S12C-Family has full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O port bits are available with Wake-Up capability from STOP or WAIT mode. The MC9S12C-Family is available in 48, 52 and 80 pin QFP packages, with the 80 Pin version pin compatible to the HCS12 B and D- Family derivatives
1.2 Features
* 16-bit HCS12 CORE - HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer's model identical to M68HC11 iii. Instruction queue iv. Enhanced indexed addressing - - - - - * * - - - * MMC (memory map and interface) INT (interrupt control) BDM (background debug mode) DBG12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer) MEBI : Multiplexed Expansion Bus Interface (available only in 80 pin package version) Up to 12-port bits available for wake up interrupt function with digital filtering 32K, 64K, 96K or 128KByte Flash EEPROM (erasable in 512-byte sectors) 2K or 4K Byte RAM
Wake-up interrupt inputs Memory options
Analog-to-Digital Converters
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
- - * - - - - - * - - - - - - - * - - - - - - * - - * - - - - -
One 8-channel module with 10-bit resolution. External conversion trigger capability Five receive and three transmit buffers Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Rx, Tx, error and wake-up Low-pass filter wake-up function Loop-back for self test operation 8-Channel Timer Each Channel Configurable as either Input Capture or Output Compare Simple PWM Mode Modulo Reset of Timer Counter 16-Bit Pulse Accumulator External Event Counting Gated Time Accumulation Programmable period and duty cycle 8-bit 6-channel or 16-bit 3-channel Separate control for each pulse width and duty cycle Center-aligned or left-aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input One asynchronous serial communications interface (SCI) One synchronous serial peripheral interface (SPI) Windowed COP watchdog, Real time interrupt, Clock monitor, Pierce or low current Colpitts oscillator Phase-locked loop clock frequency multiplier
One 1M bit per second, CAN 2.0 A, B software compatible modules
Timer Module (TIM)
6 PWM channels
Serial interfaces
CRG (Clock Reset Generator Module)
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
- - * - - - * - - - - * - - - * - - -
Limp home mode in absence of external clock Low power 0.5 to 16 MHz crystal oscillator reference clock 32MHz equivalent to 16MHz Bus Speed for single chip 32MHz equivalent to 16MHz Bus Speed in expanded bus modes Option: 50MHz equivalent to 25MHz Bus Speed Supports an input voltage range from 2.97V to 5.5V Low power mode capability Includes low voltage reset (LVR) circuitry Includes low voltage interrupt (LVI) circuitry Up to 58 I/O lines with 5V input and drive capability (80 pin package) Up to 2 dedicated 5V input only lines (IRQ, XIRQ) 5V 8 A/D converter inputs and 5V I/O Single-wire background debugTM mode (BDM) On-chip hardware breakpoints Enhanced DBG12 debug features
Operating frequency
Internal 2.5V Regulator
48-Pin LQFP, 52-Pin LQFP or 80-Pin QFP package
Development support
1.3 Modes of Operation
User modes (Expanded modes are only available in the 80 pin package version). * Normal and Emulation Operating Modes - - - - - * - - - Normal Single-Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Single-Chip Mode with active Background Debug Mode Special Test Mode (Motorola use only) Special Peripheral Mode (Motorola use only)
Special Operating Modes
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
*
Low power modes - - - Stop Mode Pseudo Stop Mode Wait Mode
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
1.4 Block Diagram
Figure 1-1 MC9S12C-Family Block Diagram
VSSR VDDR VDDX VSSX
ATD Voltage Regulator
VDDA VSSA VRH VRL AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 PW0 PW1 PW2 PW3 PW4 PW5
VDDA VSSA VRH VRL PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PJ6 PJ7 PS0 PS1 PS2 PS3 PM0 PM1 PM2 PM3 PM4 PM5
DDRAD DDRT Key Int Keypad Interrupt DDRP DDRJ DDRS DDRM
VDD2 VSS2 VDD1 VSS1 BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 TEST/VPP
32K, 64K, 96K, 128K Byte Flash 2K, 4K Byte RAM
Background MODC Debug12 Module Clock and Reset Generation Module
HCS12 CPU Timer Module
COP Watchdog Clock Monitor Periodic Interrupt
MUX PTT PTM PTS PTJ PTP
PLL
XIRQ IRQ System R/W Integration LSTRB/TAGLO Module ECLK (SIM) MODA/IPIPE0 MODB/IPIPE1 NOACC/XCLKS
DDRE
PTE
PWM Module
Multiplexed Address/Data Bus
SCI
RXD TXD
DDRA PTA
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
DDRB PTB
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
MSCAN SPI
ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8
DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8
Multiplexed Wide Bus
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
RXCAN TXCAN MISO SS MOSI SCK
Signals shown in Bold are not available on the 52 or 48 Pin Package Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package
Internal Logic 2.5V
VDD1,2 VSS1,2
I/O Driver 5V
VDDX VSSX
PLL 2.5V
VDDPLL VSSPLL
A/D Converter 5V
VDDA VSSA
VRL is bonded internally to VSSA for 52 and 48 Pin packages
Voltage Regulator 5V & I/O
VDDR VSSR
PTAD
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
1.5 Device Memory Map
Table 1-1 shows the device register map of the MC9S12C-Family after reset. The following figures ( Figure 1-2, Figure 1-2, Figure 1-3 and Figure 1-4) illustrate the full device memory map with flash and RAM. Table 1-1 Device Register Map Overview
Address
$000 - $017 $018 $019 $01A - $01B $01C - $01F $020 - $02F $030 - $033 $034 - $03F $040 - $06F $070 - $07F $080 - $09F $0A0 - $0C7 $0C8 - $0CF $0D0 - $0D7 $0D8 - $0DF $0E0 - $0FF $100 - $10F $110 - $13F $140 - $17F $180 - $23F $240 - $27F $280 - $3FF Reserved Voltage Regulator (VREG) Device ID register CORE (MEMSIZ, IRQ, HPRIO) CORE (DBG) CORE (PPAGE1) Clock and Reset Generator (CRG) Standard Timer Module16-bit 8-channels (TIM) Reserved Analog to Digital Convert (ATD) Reserved Serial Communications Interface (SCI) Reserved Serial Peripheral Interface (SPI) Pulse Width Modulator 8-bit 6 channels (PWM) Flash Control Register Reserved Motorola Scalable CAN (MSCAN) Reserved Port Integration Module (PIM) Reserved
Module
CORE (Ports A, B, E,Modes, Inits, Test)
Size
24 1 1 2 4 16 4 12 48 16 32 40 8 8 8 32 16 48 64 192 64 384
NOTES: 1. External memory paging is not supported on this device (6.1.1 PPAGE).
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$0000 $0000 $0400 $03FF $0000
1K Register Space Mappable to any 2K Boundary 16K Fixed Flash EEPROM
$3FFF $3000 $3000 $3FFF $4000 $4000 4K Bytes RAM Mappable to any 4K Boundary
16K Fixed Flash EEPROM
$7FFF $8000 $8000 16K Page Window 8 * 16K Flash EEPROM Pages
EXT
$BFFF $C000 $C000 16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF) Flash Erase Sector Size is 1024 Bytes
Figure 1-2 MC9S12C128 User configurable Memory Map
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$0000 $0000 $0400 $03FF $0000
1K Register Space Mappable to any 2K Boundary 16K Fixed Flash EEPROM
$3FFF $3000 $3000 $3FFF $4000 $4000 4K Bytes RAM Mappable to any 4K Boundary
16K Fixed Flash EEPROM
$7FFF $8000 $8000 16K Page Window 6 * 16K Flash EEPROM Pages
EXT
$BFFF $C000 $C000 16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF) Flash Erase Sector Size is 1024 Bytes
Figure 1-3 MC9S12C96 User Configurable Memory Map
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$0000 $0000 $0400 $03FF $0000
1K Register Space Mappable to any 2K Boundary 16K Fixed Flash EEPROM
$3FFF $3000 $3000 $3FFF $4000 $4000 4K Bytes RAM Mappable to any 4K Boundary
16K Fixed Flash EEPROM
$7FFF $8000 $8000 16K Page Window 4 * 16K Flash EEPROM Pages
EXT
$BFFF $C000 $C000 16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF) Flash Erase Sector Size is 512 Bytes
Figure 1-4 MC9S12C64 User Configurable Memory Map
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$0000 $0000 $0400 $03FF
1K Register Space Mappable to any 2K Boundary
$3800
$3800 $3FFF
2K Bytes RAM Mappable to any 2K Boundary
$4000
$8000
$8000 16K Page Window 2 * 16K Flash EEPROM Pages
EXT
$BFFF $C000 $C000 16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0800 - $0FFF: 2K RAM Flash Erase Sector Size is 512 Bytes
Figure 1-5 MC9S12C32 User Configurable Memory Map
1.6 Detailed Register Map
The detailed register map of the MC9S12C Family is listed in address order below.
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$0000 - $000F
Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F Name PORTA PORTB DDRA DDRB Reserved Reserved Reserved Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved
MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: NOACCE Write: Read: MODC Write: Read: PUPKE Write: Read: RDPK Write: Read: 0 Write: Read: 0 Write: Bit 6 6 6 6 6 0 0 0 0 6 6 0 MODB 0 0 0 0 Bit 5 5 5 5 5 0 0 0 0 5 5 PIPOE MODA 0 0 0 0 Bit 4 4 4 4 4 0 0 0 0 4 4 NECLK 0 PUPEE RDPE 0 0 Bit 3 3 3 3 3 0 0 0 0 3 3 LSTRE IVIS 0 0 0 0 Bit 2 2 2 2 2 0 0 0 0 2 Bit 2 RDWE 0 0 0 0 0 Bit 1 1 1 1 1 0 0 0 0 Bit 1 0 0 EMK PUPBE RDPB 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 0 0 0 0 Bit 0 0 0 EME PUPAE RDPA ESTR 0
$0010 - $0014
Address $0010 $0011 Address Name INITRM INITRG Name
MMC map 1 of 4 (HCS12 Module Mapping Control)
Bit 7 Read: RAM15 Write: Read: 0 Write: Bit 7 Bit 6 RAM14 REG14 Bit 6 Bit 5 RAM13 REG13 Bit 5 Bit 4 RAM12 REG12 Bit 4 Bit 3 RAM11 REG11 Bit 3 Bit 2 0 0 Bit 2 Bit 1 0 0 Bit 1 Bit 0 RAMHAL 0 Bit 0
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$0010 - $0014
Address $0012 $0013 $0014 Name INITEE MISC Reserved Read: Write: Read: Write: Read: Write:
MMC map 1 of 4 (HCS12 Module Mapping Control)
Bit 7 EE15 0 0 Bit 6 EE14 0 0 Bit 5 EE13 0 0 Bit 4 EE12 0 0 Bit 3 EE11 EXSTR1 0 Bit 2 0 EXSTR0 0 Bit 1 0 ROMHM 0 Bit 0 EEON ROMON 0
$0015 - $0016
Address $0015 $0016 Name ITCR ITEST Read: Write: Read: Write:
INT map 1 of 2 (HCS12 Interrupt)
Bit 7 0 INTE Bit 6 0 INTC Bit 5 0 INTA Bit 4 WRINT INT8 Bit 3 ADR3 INT6 Bit 2 ADR2 INT4 Bit 1 ADR1 INT2 Bit 0 ADR0 INT0
$0017 - $0017
Address $0017 Name Reserved Read: Write:
MMC map 2 of 4 (HCS12 Module Mapping Control)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0018 - $0018
Address $0018 Name Reserved Read: Write:
Miscellaneous Peripherals (Device User Guide)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0019 - $0019
Address $0019 Name VREGCTRL Read: Write:
VREG3V3 (Voltage Regulator)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 LVDS Bit 1 LVIE Bit 0 LVIF
$001A - $001B
Address $001A $001B Name PARTIDH PARTIDL Read: Write: Read: Write:
Miscellaneous Peripherals (Device User Guide)
Bit 7 ID15 ID7 Bit 6 ID14 ID6 Bit 5 ID13 ID5 Bit 4 ID12 ID4 Bit 3 ID11 ID3 Bit 2 ID10 ID2 Bit 1 ID9 ID1 Bit 0 ID8 ID0
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$001C - $001D
MMC map 3 of 4 (HCS12 Module Mapping Control, Device User Guide)
Bit 7 Read: reg_sw0 Write: Read: rom_sw1 Write: Bit 6 0 rom_sw0 Bit 5 eep_sw1 0 Bit 4 eep_sw0 0 Bit 3 0 0 Bit 2 ram_sw2 0 Bit 1 ram_sw1 pag_sw1 Bit 0 ram_sw0 pag_sw0
Address $001C $001D
Name MEMSIZ0 MEMSIZ1
$001E - $001E
Address $001E Name INTCR Read: Write:
MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)
Bit 7 IRQE Bit 6 IRQEN Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$001F - $001F
Address $001F Name HPRIO Read: Write:
INT map 2 of 2 (HCS12 Interrupt)
Bit 7
PSEL7
Bit 6
PSEL6
Bit 5
PSEL5
Bit 4
PSEL4
Bit 3
PSEL3
Bit 2
PSEL2
Bit 1
PSEL1
Bit 0
0
$0020 - $002F
Address $0020 $0021 $0022
$0023 $0024 $0025 $0026 $0027
DBG (including BKP) map 1 of 1 (HCS12 Debug )
Bit 7 read DBGEN write AF read write read Bit 15 write
read write read write read write read write read write Bit 7 TBF PAGSEL Bit 15 Bit 7 14 6 13 5 12 4
Name DBGC1
-
Bit 6
ARM BF Bit 14 Bit 6 0
Bit 5
TRGSEL CF Bit 13 Bit 5
Bit 4
BEGIN 0 Bit 12 Bit 4
Bit 3
DBGBRK
Bit 2
0
Bit 1
Bit 0
CAPMOD TRG
DBGSC
DBGTBH DBGTBL DBGCNT DBGCCX DBGCCH DBGCCL -
Bit 11 Bit 3 CNT
Bit 10 Bit 2
Bit 9 Bit 1
Bit 8 Bit 0
EXTCMP 11 3 10 2 9 1 RWCEN RWBEN Bit 8 Bit 0 RWC RWB
$0028 $0029 $002A
$002B
DBGC2
BKPCT0
DBGC3
BKPCT1 DBGCAX BKP0X DBGCAH BKP0H
read BKABEN FULL BDM TAGAB BKCEN TAGC write read BKAMBH BKAMBL BKBMBH BKBMBL RWAEN RWA write read PAGSEL EXTCMP write
read write Bit 15 14 13 12 11 10
9
Bit 8
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$0020 - $002F
Address
$002C $002D $002E $002F
DBG (including BKP) map 1 of 1 (HCS12 Debug )
Bit 7
read write read write read write read write Bit 7 PAGSEL Bit 15 Bit 7 14 6 13 5 12 4
Name
DBGCAL BKP0L DBGCBX BKP1X DBGCBH BKP1H DBGCBL BKP1L
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
EXTCMP 11 3 10 2 9 1 Bit 8 Bit 0
$0030 - $0031
Address $0030 $0031 Name PPAGE Reserved Read: Write: Read: Write:
MMC map 4 of 4 (HCS12 Module Mapping Control)
Bit 7 0 0 Bit 6 0 0 Bit 5 PIX5 0 Bit 4 PIX4 0 Bit 3 PIX3 0 Bit 2 PIX2 0 Bit 1 PIX1 0 Bit 0 PIX0 0
$0032 - $0033
Address $0032 $0033 Name PORTK1 DDRK(1) Read: Write: Read: Write:
MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)
Bit 7 Bit 7 Bit 7 Bit 6 6 6 Bit 5 5 5 Bit 4 4 4 Bit 3 3 3 Bit 2 2 2 Bit 1 1 1 Bit 0 Bit 0 Bit 0
NOTES: 1. Only applicable in special emulation-only bond outs, for emulation of extended memory map.
$0034 - $003F
Address $0034 $0035 $0036 $0037 $0038 $0039 $003A Name SYNR REFDV CTFLG TEST ONLY CRGFLG CRGINT CLKSEL PLLCTL
CRG (Clock and Reset Generator)
Read: Write: Read: 0 Write: Read: TOUT7 Write: Read: RTIF Write: Read: RTIE Write: Read: PLLSEL Write: Read: CME Write: Bit 7 0 Bit 6 0 0 TOUT6 PROF 0 PSTP PLLON Bit 5 SYN5 0 TOUT5 0 0 SYSWAI AUTO Bit 4 SYN4 0 TOUT4 LOCKIF LOCKIE ROAWAI ACQ Bit 3 SYN3 REFDV3 TOUT3 LOCK 0 PLLWAI 0 Bit 2 SYN2 REFDV2 TOUT2 TRACK 0 CWAI PRE Bit 1 SYN1 REFDV1 TOUT1 SCMIF SCMIE RTIWAI PCE Bit 0 SYN0 REFDV0 TOUT0 SCM 0 COPWAI SCME
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$0034 - $003F
Address $003B $003C $003D $003E $003F Name RTICTL COPCTL FORBYP TEST ONLY CTCTL TEST ONLY ARMCOP
CRG (Clock and Reset Generator)
Read: Write: Read: WCOP Write: Read: RTIBYP Write: Read: TCTL7 Write: Read: 0 Write: Bit 7 Bit 7 0 Bit 6 RTR6 RSBCK COPBYP TCTL6 0 6 Bit 5 RTR5 0 0 TCTL5 0 5 Bit 4 RTR4 0 PLLBYP TCTL4 0 4 Bit 3 RTR3 0 0 TCLT3 0 3 Bit 2 RTR2 CR2 0 TCTL2 0 2 Bit 1 RTR1 CR1 FCM TCTL1 0 1 Bit 0 RTR0 CR0 0 TCTL0 0 Bit 0
$0040 - $006F
Address $0040 $0041 $0042 $0043 $0044 $0045 $0046 $0047 $0048 $0049 $004A $004B $004C $004D $004E $004F Name TIOS CFORC OC7M OC7D TCNT (hi) TCNT (lo) TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
TIM (Timer 16 Bit 8 Channels)
Bit 7 IOS7
0 FOC7
Bit 6 IOS6
0 FOC6
Bit 5 IOS5
0 FOC5
Bit 4 IOS4
0 FOC4
Bit 3 IOS3
0 FOC3
Bit 2 IOS2
0 FOC2
Bit 1 IOS1
0 FOC1
Bit 0 IOS0
0 FOC0
OC7M7 OC7D7
Bit 15 Bit 7
OC7M6 OC7D6
14 6
OC7M5 OC7D5
13 5
OC7M4 OC7D4
12 4
OC7M3 OC7D3
11 3
OC7M2 OC7D2
10 2
OC7M1 OC7D1
9 1
OC7M0 OC7D0
Bit 8 Bit 0
TEN TOV7 OM7 OM3 EDG7B EDG3B C7I TOI C7F TOF
TSWAI TOV6 OL7 OL3 EDG7A EDG3A C6I 0 C6F 0
TSFRZ TOV5 OM6 OM2 EDG6B EDG2B C5I 0 C5F 0
TFFCA TOV4 OL6 OL2 EDG6A EDG2A C4I 0 C4F 0
0 TOV3 OM5 OM1 EDG5B EDG1B C3I TCRE C3F 0
0 TOV2 OL5 OL1 EDG5A EDG1A C2I PR2 C2F 0
0 TOV1 OM4 OM0 EDG4B EDG0B C1I PR1 C1F 0
0 TOV0 OL4 OL0 EDG4A EDG0A C0I PR0 C0F 0
33
Device User Guide -- 9S12C-FamilyDGV1/D V01.01 Address $0050 $0051 $0052 $0053 $0054 $0055 $0056 $0057 $0058 $0059 $005A $005B $005C $005D $005E $005F $0060 $0061 $0062 $0063 $0064 $0065 $0066 $0067 Name TC0 (hi) TC0 (lo) TC1 (hi) TC1 (lo) TC2 (hi) TC2 (lo) TC3 (hi) TC3 (lo) TC4 (hi) TC4 (lo) TC5 (hi) TC5 (lo) TC6 (hi) TC6 (lo) TC7 (hi) TC7 (lo) PACTL PAFLG PACNT (hi) PACNT (lo) Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7
Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 0
Bit 6
14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 PAEN
Bit 5
13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 PAMOD
Bit 4
12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 PEDGE
Bit 3
11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 CLK1
Bit 2
10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 CLK0
Bit 1
9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 PAOVI
Bit 0
Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 PAI
0
Bit 15
0
14
0
13
0
12
0
11
0
10
PAOVF
9
PAIF
Bit 8
Bit 7 0 0 0 0
6 0 0 0 0
5 0 0 0 0
4 0 0 0 0
3 0 0 0 0
2 0 0 0 0
1 0 0 0 0
Bit 0 0 0 0 0
34
Device User Guide -- 9S12C-FamilyDGV1/D V01.01 Address $0068 $0069 $006A $006B $006C $006D $006E $006F Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 0 0 0 0 0 0 0 0 Bit 6 0 0 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 Bit 4 0 0 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 0 0 Bit 2 0 0 0 0 0 0 0 0 Bit 1 0 0 0 0 0 0 0 0 Bit 0 0 0 0 0 0 0 0 0
$0070 - $007F
$0070 - $007F Reserved Read: Write:
Reserved
0 0 0 0 0 0 0 0
$0080 - $009F
Address $0080 $0081 $0082 $0083 $0084 $0085 $0086 $0087 $0088 $0089 $008A Name ATDCTL0 ATDCTL1 ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5 ATDSTAT0 Reserved ATDTEST0 ATDTEST1 Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
ATD (Analog to Digital Converter 10 Bit 8 Channel)
Bit 7 0 0 ADPU 0 SRES8 DJM SCF 0 0 0 0 Bit 6 0 0 AFFC S8C SMP1 DSGN 0 0 0 0 0 Bit 5 0 0 AWAI S4C SMP0 SCAN ETORF 0 0 0 0 Bit 4 0 0 ETRIGLE S2C PRS4 MULT FIFOR 0 0 0 0 Bit 3 0 0 ETRIGP S1C PRS3 0 0 0 0 0 0 Bit 2 0 0 ETRIG FIFO PRS2 CC CC2 0 0 0 0 Bit 1 0 0 ASCIE FRZ1 PRS1 CB CC1 0 0 0 0 Bit 0 0 0 ASCIF FRZ0 PRS0 CA CC0 0 0 SC 0
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$0080 - $009F
Address $008B $008C $008D $008E $008F $0090 $0091 $0092 $0093 $0094 $0095 $0096 $0097 $0098 $0099 $009A $009B $009C $009D $009E $009F Name ATDSTAT1 Reserved ATDDIEN Reserved PORTAD0 ATDDR0H ATDDR0L ATDDR1H ATDDR1L ATDDR2H ATDDR2L ATDDR3H ATDDR3L ATDDR4H ATDDR4L ATDDR5H ATDDR5L ATDDR6H ATDDR6L ATDDR7H ATDDR7L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
ATD (Analog to Digital Converter 10 Bit 8 Channel)
Bit 7 CCF7 0 Bit 7 0 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 CCF6 0 6 0 6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 Bit 5 CCF5 0 5 0 5 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 Bit 4 CCF4 0 4 0 4 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 Bit 3 CCF3 0 3 0 3 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 Bit 2 CCF2 0 2 0 2 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 Bit 1 CCF1 0 1 0 1 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 Bit 0 CCF0 0 Bit 0 0 BIT 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0
$00A0 - $00C7
$00A0 - $00C7 Reserved Read: Write:
Reserved
0 0 0 0 0 0 0 0
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$00C8 - $00CF
Address $00C8 $00C9 $00CA $00CB $00CC $00CD $00CE $00CF Name SCIBDH SCIBDL SCICR1 SCICR2 SCISR1 SCISR2 SCIDRH SCIDRL
SCI (Asynchronous Serial Interface)
Bit 7 0 Read: Write: Read: SBR7 Write: Read: LOOPS Write: Read: TIE Write: Read: TDRE Write: Read: 0 Write: Read: R8 Write: Read: R7 Write: T7 Bit 6
0
Bit 5
0
Bit 4
SBR12
Bit 3
SBR11
Bit 2
SBR10
Bit 1
SBR9
Bit 0
SBR8
SBR6 SCISWAI TCIE TC 0 T8 R6 T6
SBR5 RSRC RIE RDRF 0 0 R5 T5
SBR4 M ILIE IDLE 0 0 R4 T4
SBR3 WAKE TE OR 0 0 R3 T3
SBR2 ILT RE NF BRK13 0 R2 T2
SBR1 PE RWU FE TXDIR 0 R1 T1
SBR0 PT SBK PF RAF 0 R0 T0
$00D0 - $00D7
$00D0 - $00D7 Reserved Read: Write:
Reserved
0 0 0 0 0 0 0 0
$00D8 - $00DF
Address $00D8 $00D9 $00DA $00DB $00DC $00DD $00DE $00DF Name SPICR1 SPICR2 SPIBR SPISR Reserved SPIDR Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
SPI (Serial Peripheral Interface)
Bit 7 SPIE 0 0 SPIF 0 Bit7 0 0 Bit 6 SPE 0 SPPR2 0 0 6 0 0 Bit 5 SPTIE 0 SPPR1 SPTEF 0 5 0 0 Bit 4 MSTR Bit 3 CPOL Bit 2 CPHA 0 SPR2 0 0 2 0 0 Bit 1 SSOE SPISWAI SPR1 0 0 1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 Bit0 0 0
MODFEN BIDIROE SPPR0 MODF 0 4 0 0 0 0 0 3 0 0
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$00E0 - $00FF
Address $00E0 $00E1 $00E2 $00E3 $00E4 $00E5 $00E6 $00E7 $00E8 $00E9 $00EA $00EB $00EC $00ED $00EE $00EF $00F0 $00F1 $00F2 $00F3 $00F4 $00F5 $00F6 Name PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL PWMTST Test Only PWMPRSC PWMSCLA PWMSCLB PWMSCNTA PWMSCNTB PWMCNT0 PWMCNT1 PWMCNT2 PWMCNT3 PWMCNT4 PWMCNT5 PWMPER0 PWMPER1 PWMPER2 PWMPER3 PWMPER4 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
PWM (Pulse Width Modulator)
Bit 7 0 0 0 0 0 0 0 0 Bit 7 Bit 7 0 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 6 0 0 0 PCKB2 0 CON45 0 0 6 6 0 0 6 0 6 0 6 0 6 0 6 0 6 0 6 6 6 6 6 Bit 5 PWME5 PPOL5 PCLK5 PCKB1 CAE5 CON23 0 0 5 5 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 5 5 5 Bit 4 PWME4 PPOL4 PCLK4 PCKB0 CAE4 CON01 0 0 4 4 0 0 4 0 4 0 4 0 4 0 4 0 4 0 4 4 4 4 4 Bit 3 PWME3 PPOL3 PCLK3 0 CAE3 PSWAI 0 0 3 3 0 0 3 0 3 0 3 0 3 0 3 0 3 0 3 3 3 3 3 Bit 2 PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ 0 0 2 2 0 0 2 0 2 0 2 0 2 0 2 0 2 0 2 2 2 2 2 Bit 1 PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 Bit 0 PWME0 PPOL0 PCLK0 PCKA0 CAE0
0
0 0 Bit 0 Bit 0 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
38
Device User Guide -- 9S12C-FamilyDGV1/D V01.01 Address $00F7 $00F8 $00F9 $00FA $00FB $00FC $00FD $00FE $00FF Name PWMPER5 PWMDTY0 PWMDTY1 PWMDTY2 PWMDTY3 PWMDTY4 PWMDTY5 Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 0 0 Bit 6 6 6 6 6 6 6 6 0 0 Bit 5 5 5 5 5 5 5 5 0 0 Bit 4 4 4 4 4 4 4 4 0 0 Bit 3 3 3 3 3 3 3 3 0 0 Bit 2 2 2 2 2 2 2 2 0 0 Bit 1 1 1 1 1 1 1 1 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 0 0
$0100 - $010F
Address $0100 $0101 $0102 $0103 $0104 $0105 $0106 $0107 $0108 $0109 $010A $010B Name FCLKDIV FSEC FTSTMOD FCNFG FPROT
FSTAT
Flash Control Register
Bit 7 Read: FDIVLD Write: Read: KEYEN1 Write: Read: 0 Write: Read: CBEIE Write: Read: FPOPEN Write: Read: CBEIF Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Bit 6 PRDIV8 KEYEN0 0 CCIE NV6 CCIF CMDB6 0 0 0 0 0 Bit 5 FDIV5 NV5 0 KEYACC FPHDIS PVIOL CMDB5 0 0 0 0 0 Bit 4 FDIV4 NV4 WRALL 0 FPHS1 ACCERR 0 0 0 0 0 0 Bit 3 FDIV3 NV3 0 0 FPHS0 0 0 0 0 0 0 0 Bit 2 FDIV2 NV2 0 0 FPLDIS BLANK CMDB2 0 0 0 0 0 Bit 1 FDIV1 SEC1 0 BKSEL1 FPLS1 0 0 0 0 0 0 0 Bit 0 FDIV0 SEC0 0 BKSEL0 FPLS0 0 CMDB0 0 0 0 0 0
FCMD Reserved for Factory Test Reserved for Factory Test Reserved for Factory Test Reserved for Factory Test Reserved for Factory Test
39
Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$0100 - $010F
Address $010C $010D $010E $010F Name Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write:
Flash Control Register
Bit 7 0 0 0 0 Bit 6 0 0 0 0 Bit 5 0 0 0 0 Bit 4 0 0 0 0 Bit 3 0 0 0 0 Bit 2 0 0 0 0 Bit 1 0 0 0 0 Bit 0 0 0 0 0
$0110 - $013F
$0110 - $003F Reserved Read: Write:
Reserved
0 0 0 0 0 0 0 0
$0140 - $017F
Address $0140 $0141 $0142 $0143 $0144 $0145 $0146 $0147 $0148 $0149 $014A $014B $014C $014D Name CANCTL0 CANCTL1 CANBTR0 CANBTR1 CANRFLG CANRIER CANTFLG CANTIER CANTARQ CANTAAK CANTBSEL CANIDAC Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
CAN (Motorola Scalable CAN - MSCAN)
Bit 7
RXFRM CANE
Bit 6
RXACT
Bit 5
CSWAI LOOPB
Bit 4
SYNCH
Bit 3
TIME 0
Bit 2
WUPE WUPM
Bit 1
SLPRQ SLPAK
Bit 0
INITRQ INITAK
CLKSRC
LISTEN
SJW1 SAMP WUPIF WUPIE
0
SJW0 TSEG22 CSCIF CSCIE
0
BRP5 TSEG21 RSTAT1
BRP4 TSEG20 RSTAT0
BRP3 TSEG13 TSTAT1
BRP2 TSEG12 TSTAT0
BRP1 TSEG11 OVRIF OVRIE
TXE1
BRP0 TSEG10 RXF RXFIE
TXE0
RSTATE1 RSTATE0 TSTATE1 TSTATE0
0 0 0 TXE2
0
0
0
0
0
0
0
0
0
0
TXEIE2
ABTRQ2
TXEIE1
ABTRQ1
TXEIE0
ABTRQ0
0
0
0
0
0
0
0
0
0
0
ABTAK2
TX2
ABTAK1
TX1
ABTAK0
TX0
0 0 0
0 0 0
IDAM1 0 0
IDAM0 0 0
0 0 0
IDHIT2 0 0
IDHIT1 0 0
IDHIT0 0 0
40
Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$0140 - $017F
Address $014E $014F $0150 $0153 $0154 $0157 $0158 $015B $015C $015F $0160 $016F $0170 $017F Name CANRXERR CANTXERR CANIDAR0 CANIDAR3 CANIDMR0 CANIDMR3 CANIDAR4 CANIDAR7 CANIDMR4 CANIDMR7 CANRXFG CANTXFG
CAN (Motorola Scalable CAN - MSCAN)
Bit 7 Read: RXERR7 Write: Read: TXERR7 Write: Read: AC7 Write: Read: AM7 Write: Read: AC7 Write: Read: AM7 Write: Read: Write: Read: Write: Bit 6
RXERR6 TXERR6
Bit 5
RXERR5 TXERR5
Bit 4
RXERR4 TXERR4
Bit 3
RXERR3 TXERR3
Bit 2
RXERR2 TXERR2
Bit 1
RXERR1 TXERR1
Bit 0
RXERR0 TXERR0
AC6 AM6 AC6 AM6
AC5 AM5 AC5 AM5
AC4 AM4 AC4 AM4
AC3 AM3 AC3 AM3
AC2 AM2 AC2 AM2
AC1 AM1 AC1 AM1
AC0 AM0 AC0 AM0
FOREGROUND RECEIVE BUFFER see Table 1-2 FOREGROUND TRANSMIT BUFFER see Table 1-2
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address $xxx0 Name Extended ID Standard ID CANxRIDR0 Extended ID Standard ID CANxRIDR1 Extended ID Standard ID CANxRIDR2 Extended ID Standard ID CANxRIDR3 CANxRDSR0 CANxRDSR7 Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Write: Read: CANRxDLR Write: Read: Reserved Write: Read: CANxRTSRH Write: Read: CANxRTSRL Write: Extended ID Read: CANxTIDR0 Write: Standard ID Read: Write: Bit 7 ID28 ID10 ID20 ID2 ID14 Bit 6 ID27 ID9 ID19 ID1 ID13 Bit 5 ID26 ID8 ID18 ID0 ID12 Bit 4 ID25 ID7 SRR=1 RTR ID11 Bit 3 ID24 ID6 IDE=1 IDE=0 ID10 Bit 2 ID23 ID5 ID17 Bit 1 ID22 ID4 ID16 Bit 0 ID21 ID3 ID15
$xxx1
ID9
ID8
ID7
$xxx2
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$xxx3 $xxx4$xxxB $xxxC $xxxD $xxxE $xxxF
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2
DB1 DLC1
DB0 DLC0
TSR15 TSR7 ID28 ID10
TSR14 TSR6 ID27 ID9
TSR13 TSR5 ID26 ID8
TSR12 TSR4 ID25 ID7
TSR11 TSR3 ID24 ID6
TSR10 TSR2 ID23 ID5
TSR9 TSR1 ID22 ID4
TSR8 TSR0 ID21 ID3
$xx10
41
Device User Guide -- 9S12C-FamilyDGV1/D V01.01
Address $xx11 Name Extended ID CANxTIDR1 Standard ID Extended ID CANxTIDR2 Standard ID Extended ID CANxTIDR3 Standard ID CANxTDSR0 CANxTDSR7 CANxTDLR CONxTTBPR CANxTTSRH CANxTTSRL Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: ID20 ID2 ID14 Bit 6 ID19 ID1 ID13 Bit 5 ID18 ID0 ID12 Bit 4 SRR=1 RTR ID11 Bit 3 IDE=1 IDE=0 ID10 ID9 ID8 ID7 Bit 2 ID17 Bit 1 ID16 Bit 0 ID15
$xx12
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$xx13 $xx14$xx1B $xx1C $xx1D $xx1E $xx1F
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2 PRIO2 TSR10 TSR2
DB1 DLC1 PRIO1 TSR9 TSR1
DB0 DLC0 PRIO0 TSR8 TSR0
PRIO7 TSR15 TSR7
PRIO6 TSR14 TSR6
PRIO5 TSR13 TSR5
PRIO4 TSR12 TSR4
PRIO3 TSR11 TSR3
$0180 - $023F
$0180 - $023F Reserved Read: Write:
Reserved
0 0 0 0 0 0 0 0
$0240 - $027F
Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
PIM (Port Interface Module)
$0240 $0241 $0242 $0243 $0244 $0245 $0246 $0247 $0248
PTT PTIT DDRT RDRT PERT PPST Reserved MODRR PTS
PTT7 PTIT7 DDRT7 RDRT7 PERT7 PPST7 0 0 0
PTT6 PTIT6 DDRT7 RDRT6 PERT6 PPST6 0 0 0
PTT5 PTIT5 DDRT5 RDRT5 PERT5 PPST5 0 0 0
PTT4 PTIT4 DDRT4 RDRT4 PERT4 PPST4 0
PTT3 PTIT3 DDRT3 RDRT3 PERT3 PPST3 0
PTT2 PTIT2 DDRT2 RDRT2 PERT2 PPST2 0
PTT1 PTIT1 DDRT1 RDRT1 PERT1 PPST1 0
PTT0 PTIT0 DDRT0 RDRT0 PERT0 PPST0 0
MODRR4 MODRR3 MODRR2 MODRR1 MODRR0
0
PTS3
PTS2
PTS1
PTS0
42
Device User Guide -- 9S12C-FamilyDGV1/D V01.01 Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: PTP7 Write: Read: PTIP7 Write: Read: DDRP7 Write: Read: RDRP7 Write: Read: PERP7 Write: Read: PPSP7 Write: Read: PIEP7 Write: Read: PIFP7 Write: Read: 0 Write: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTP6 PTIP6 DDRP7 RDRP6 PERP6 PPSP6 PIEP6 PIFP6 0 0 0 0 0 0 0 0 PTM5 PTIM5 DDRM5 RDRM5 PERM5 PPSM5 WOMM5 0 PTP5 PTIP5 DDRP5 RDRP5 PERP5 PPSP5 PIEP5 PIFP5 0 0 0 0 0 0 0 0 PTM4 PTIM4 DDRM4 RDRM4 PERM4 PPSM4 WOMM4 0 PTP4 PTIP4 DDRP4 RDRP4 PERP4 PPSP4 PIEP4 PIFP4 0 PTIS3 DDRS3 RDRS3 PERS3 PPSS3 WOMS3 0 PTM3 PTIM3 DDRM3 RDRM3 PERM3 PPSM3 WOMM3 0 PTP3 PTIP3 DDRP3 RDRP3 PERP3 PPSP3 PIEP3 PIFP3 0 PTIS2 DDRS2 RDRS2 PERS2 PPSS2 WOMS2 0 PTM2 PTIM2 DDRM2 RDRM2 PERM2 PPSM2 WOMM2 0 PTP2 PTIP2 DDRP2 RDRP2 PERP2 PPSP2 PIEP2 PIFP2 0 PTIS1 DDRS1 RDRS1 PERS1 PPSS1 WOMS1 0 PTM1 PTIM1 DDRM1 RDRM1 PERM1 PPSM1 WOMM1 0 PTP1 PTIP1 DDRP1 RDRP1 PERP1 PPSP1 PIEP1 PIFP1 0 PTIS0 DDRS0 RDRS0 PERS0 PPSS0 WOMS0 0 PTM0 PTIM0 DDRM0 RDRM0 PERM0 PPSM0 WOMM0 0 PTP0 PTIP0 DDRP0 RDRP0 PERP0 PPSS0 PIEP0 PIFP0 0
$0249 $024A $024B $024C $024D $024E $024F $0250 $0251 $0252 $0253 $0254 $0255 $0256 $0257 $0258 $0259 $025A $025B $025C $025D $025E $025F $0260
PTIS DDRS RDRS PERS PPSS WOMS Reserved PTM PTIM DDRM RDRM PERM PPSM WOMM Reserved PTP PTIP DDRP RDRP PERP PPSP PIEP PIFP Reserved
43
Device User Guide -- 9S12C-FamilyDGV1/D V01.01 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: 0 0 0 0 0 0 0 PTJ7 PTIJ7 DDRJ7 RDRJ7 PERJ7 PPSJ7 PIEJ7 PIFJ7
PTAD7 PTIAD7
$0261 $0262 $0263 $0264 $0265 $0266 $0267 $0268 $0269 $026A $026B $026C $026D $026E $026F $0270 $0271 $0272 $0273 $0274 $0275 $0276$027F
Reserved Reserved Reserved Reserved Reserved Reserved Reserved PTJ PTIJ DDRJ RDRJ PERJ PPSJ PIEJ PIFJ PTAD PTIAD DDRAD RDRAD PERAD PPSAD Reserved
0 0 0 0 0 0 0 PTJ6 PTIJ6 DDRJ7 RDRJ6 PERJ6 PPSJ6 PIEJ6 PIFJ6
PTAD6 PTIAD6
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PTAD5 PTIAD5
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PTAD4 PTIAD4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PTAD3 PTIAD3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PTAD2 PTIAD2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PTAD1 PTIAD1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PTAD0 PTIJ7
DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0 RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0
Read: PERAD7 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0 Write:
Read: PPSAD7 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0 Write: Read: 0 0 0 0 0 0 0 0 Write:
44
Device User Guide -- 9S12C-FamilyDGV1/D V01.01
$0280 - $03FF
Address Name Read: $0280 Reserved - $2FF Write: Read: $0300 Unimplemented $03FF Write:
Reserved space
Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0
1.7 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned part ID numbers. Table 1-3 Assigned Part ID Numbers
Device MC9S12C32 MC9S12C32 MC9S12C64 MC9S12C96 MC9S12C128 MC9S12C128 Mask Set Number 0L45J 1L45J TBD TBD 0L09S 1L09S Part ID1 $3300 $3300 TBD TBD $3100 $3101
NOTES: 1. The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor - non full - mask set revision
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset). Table 1-4 shows the read-only values of these registers. Refer to Module Mapping and Control (MMC) Block Guide for further details. Table 1-4 Memory size registers
Device MC9S12C32 MC9S12C32 MC9S12C64 MC9S12C64 MC9S12C96 MC9S12C96 MC9S12C128 MC9S12C128 Register name MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 Value $00 $80 $01 $C0 $01 $C0 $01 $C0
45
Device User Guide -- 9S12C-FamilyDGV1/D V01.01
Section 2 Signal Description
2.1 Device Pinout
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PP4/KWP4/PW4 PP5/KWP5/PW5 PP7/KWP7 VDDX VSSX PM0/RXCAN PM1/TXCAN PM2/MISO PM3/SS PM4/MOSI PM5/SCK PJ6/KWJ6 PJ7/KWJ7 PP6/KWP6/ROMCTL PS3 PS2 PS1/TXD PS0/RXD VSSA VRL PW3/KWP3/PP3 PW2/KWP2/PP2 PW1/KWP1/PP1 PW0/KWP0/PP0 PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 PW4/IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
MC9S12C-Family
80 QFP
VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Signals shown in Bold are not available on the 52 or 48 Pin Package Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package
Figure 2-1 Pin Assignments in 80 QFP for MC9S12C-Family
46
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST/VPP LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Device User Guide -- 9S12C-FamilyDGV1/D V01.01
PP4/KWP4/PW4
PP5/KWP5/PW5
PM0/RXCAN
PM1/TXCAN
PM2/MISO
PM4/MOSI
PM5/SCK 43
52
51
50
49
48
47
46
45
44
42
41
40
PS0/RXD VSSA
PS1/TXD
PM3/SS
VDDX
VSSX
PW3/KWP3/PP3 PW0/IOC0/PT0
PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 PW4/IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD PB4
1 2 3 4 5 6 7 8 9 10 11 12 13
39 38 37 36 35 34
VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00
MC9S12C-Family
52 QFP
33 32 31 30 29 28 27
PA2 PA1
PA0
14
15
16
17
18
19
20
21
22
23
24
25
VDDR
RESET
VDDPLL
EXTAL
VSSR
XTAL
XFC
* Signals shown in Bold italic are not available on the 48 Pin Package
Figure 2-2 Pin assignments in 52 LQFP for MC9S12C-Family
XCLKS/PE7
TEST/VPP IRQ/PE1 XIRQ/PE0
ECLK/PE4
VSSPLL
26
47
Device User Guide -- 9S12C-FamilyDGV1/D V01.01
PM0/RXCAN
PM1/TXCAN
PP5/KWP5
PM2/MISO
PM4/MOSI
PM5/SCK 40
48
47
46
45
44
43
42
41
39
38
PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 PW4/IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD PB4
37
PS0/RXD VSSA
PS1/TXD
PM3/SS
VDDX
VSSX
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32
VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 PA0 XIRQ/PE0
MC9S12C-Family
48 LQFP
31 30 29 28 27 26 25
13
14
15
16
17
18
19
20
21
22 XTAL
23
VDDR
XFC
RESET
VDDPLL
EXTAL
VSSR
Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C-Family
48
XCLKS/PE7
TEST/VPP IRQ/PE1
ECLK/PE4
VSSPLL
24
Device User Guide -- 9S12C-FamilyDGV1/D V01.01
2.2 Signal Properties Summary
Table 2-1 Signal Properties
Pin Name Pin Name Pin Name Power Function 1 Function 2 Function 3 Domain
EXTAL XTAL RESET XFC TEST BKGD PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PA[7:3] -- -- -- -- VPP MODC NOACC IPIPE1 IPIPE0 ECLK LSTRB R/W IRQ XIRQ ADDR[15:1/ DATA[15:1] -- -- -- -- -- TAGHI XCLKS MODB MODA -- TAGLO -- -- -- -- VDDPLL VDDPLL VDDX VDDPLL VSSX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX
Internal Pull Resistor
CTRL NA NA None NA NA Up PUCR Reset State NA NA None NA NA Up Up Oscillator pins External reset pin PLL loop filter pin Test pin only
Description
Background debug, mode pin, tag signal high Port E I/O pin, access, clock select Port E I/O pin and pipe status Port E I/O pin and pipe status Port E I/O pin, bus clock output Port E I/O pin, low strobe, tag signal low Port E I/O pin, R/W in expanded modes Port E input, external interrupt pin Port E input, non-maskable interrupt pin
While RESET pin is low: Down While RESET pin is low: Down PUCR PUCR PUCR PUCR PUCR PUCR Mode Dep1 Mode Dep(1) Mode Dep(1) Up Up
Disabled Port A I/O pin & multiplexed address/data
PA[2:1]
PA[0] PB[7:5] PB[4] PB[3:0] PAD[7:0] PP[7] PP[6] PP[5]
ADDR[10:9/ DATA[10:9]
ADDR[8]/ DATA[8] ADDR[7:5]/ DATA[7:5] ADDR[4]/ DATA[4] ADDR[3:0]/ DATA[3:0] AN[7:0] KWP[7] KWP[6] KWP[5]
--
-- -- -- -- -- -- ROMCTL PW5
VDDX
VDDX VDDX VDDX VDDX VDDA VDDX VDDX VDDX
PUCR
PUCR PUCR PUCR PUCR
Disabled Port A I/O pin & multiplexed address/data
Disabled Port A I/O pin & multiplexed address/data Disabled Port B I/O pin & multiplexed address/data Disabled Port B I/O pin & multiplexed address/data Disabled Port B I/O pin & multiplexed address/data
PERAD/P Disabled Port AD I/O pins and ATD inputs PSAD PERP/ PPSP PERP/ PPSP PERP/ PPSP Disabled Port P I/O Pins and keypad wake-up Disabled Port P I/O Pins, keypad wake-up and ROMON enable.
Disabled Port P I/O Pin, keypad wake-up, PW5 output
PP[4:3]
KWP[4:3]
PW[4:3]
VDDX
PERP/ PPSP
Disabled Port P I/O Pin, keypad wake-up, PWM output
49
Device User Guide -- 9S12C-FamilyDGV1/D V01.01 Internal Pull Resistor
CTRL PERP/ PPSP PERJ/ PPSJ PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERS/ PPSS PERS/ PPSS PERS/ PPSS PERT/ PPST PERT/ PPST Reset State
Pin Name Pin Name Pin Name Power Function 1 Function 2 Function 3 Domain
PP[2:0] PJ[7:6] PM5 PM4 PM3 PM2 PM1 PM0 PS[3:2] PS1 PS0 PT[7:5] PT[4:0] KWP[2:0] KWJ[7:6] SCK MOSI SS MISO TXCAN RXCAN -- TXD RXD IOC[7:5] IOC[4:0] PW[2:0] -- -- -- -- -- -- -- -- -- -- -- PW[4:0] VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX
Description
Disabled Port P I/O Pins, keypad wake-up, PWM outputs Disabled Port J I/O Pins and keypad wake-up Disabled Port M I/O Pin and SPI SCK signal Disabled Port M I/O Pin and SPI MOSI signal Disabled Port M I/O Pin and SPI SS signal Disabled Port M I/O Pin and SPI MISO signal Disabled Port M I/O Pin and CAN transmit signal Disabled Port M I/O Pin and CAN receive signal Up Up Up Port S I/O Pins Port S I/O Pin and SCI transmit signal Port S I/O Pin and SCI receive signal
Disabled Port T I/O Pins shared with timer (TIM) Disabled Port T I/O Pins shared with timer and PWM
NOTES: 1. The PortE output buffer enable signal control at reset is determined by the PEAR register and is mode dependent.. E.g.. in special test mode RDWE=LSTRE=1 which enables the PE[3:2] output buffers and disables the pull-ups.. Refer to S12_MEBI user guide for PEAR register details..
2.2.1 Pin Initialization for 48 & 52 Pin LQFP bond-out versions
Not Bonded Pins If the port pins are not bonded out in the chosen package the user should initialize the registers to be inputs with enabled pull resistance to avoid excess current consumption. This applies to the following pins: (48LQFP): Port A[7:1], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[4:0], Port J[7:6], PortS[3:2] (52LQFP): Port A[7:3], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[2:0], Port J[7:6], PortS[3:2]
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2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL -- Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET -- External Reset Pin
RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or COP watchdog circuit. External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one within 32 ECLK cycles after the low drive is released. Upon detection of any reset, an internal circuit drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal processing.
2.3.3 TEST / VPP -- Test Pin
This pin is reserved for test and must be tied to VSS in all applications.
2.3.4 XFC -- PLL Loop Filter Pin
Dedicated pin used to create the PLL loop filter. See CRG BUG for more detailed information.PLL loop filter. Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC R0 MCU CS VDDPLL VDDPLL
CP
Figure 2-4 PLL Loop Filter Connections
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2.3.5 BKGD / TAGHI / MODC -- Background Debug, Tag High & Mode Pin
The BKGD / TAGHI / MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. It is also used as a MCU operating mode select pin at the rising edge during reset, when the state of this pin is latched to the MODC bit.
2.3.6 PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins
PA7-PA0 are general purpose input or output pins, . In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PA[7:1] pins are not available in the 48 package version. PA[7:3] are not available in the 52 pin package version.
2.3.7 PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PB[7:5] and PB[3:0] pins are not available in the 48 nor 52 pin package version.
2.3.8 PE7 / NOACC / XCLKS -- Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or "free" cycle. This signal will assert when the CPU is not using the bus.The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator. If input is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL. Since this pin is an
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input with a pull-up device during reset, if the pin is left floating, the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL.
EXTAL CDC * MCU XTAL C2 VSSPLL * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal .Please contact the crystal manufacturer for crystal DC C1 Crystal or ceramic resonator
Figure 2-5 Colpitts Oscillator Connections (PE7=1)
Figure 2-6 Pierce Oscillator Connections (PE7=0)
EXTAL
C1
MCU RS
*
RB
Crystal or ceramic resonator C2
XTAL
VSSPLL
* Rs can be zero (shorted) when use with higher frequency crystals. Refer to manufacturer's data.
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Figure 2-7 External Clock Connections (PE7=0)
EXTAL
MCU
CMOS-COMPATIBLE EXTERNAL OSCILLATOR (VDDPLL-Level)
XTAL
not connected
2.3.9 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1}. This pin is an input with a pull-down device which is only active when RESET is low. PE[6] is not available in the 48 / 52 pin package versions.
2.3.10 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0}. This pin is an input with a pull-down device which is only active when RESET is low. This pin is not available in the 48 / 52 pin package versions.
2.3.11 PE4 / ECLK-- Port E I/O Pin [4] / E-Clock Output
ECLK is the output connection for the internal bus clock. It is used to demultiplex the address and data in expanded modes and is used as a timing reference. ECLK frequency is equal to 1/2 the crystal frequency out of reset. The ECLK pin is initially configured as ECLK output with stretch in all expanded modes. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. All clocks, including the E clock, are halted when the MCU is in STOP mode. It is possible to configure the MCU to interface to slow external memory. ECLK can be stretched for such accesses. Reference the MISC register (EXSTR[1:0] bits) for more information. In normal expanded narrow mode, the E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. Alternatively PE4 can be used as a general purpose input or output pin.
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2.3.12 PE3 / LSTRB -- Port E I/O Pin [3] / Low-Byte Strobe (LSTRB)
In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of reset. If the strobe function is required, it should be enabled by setting the LSTRE bit in the PEAR register. This signal is used in write operations. Therefore external low byte writes will not be possible until this function is enabled. This pin is also used as TAGLO in Special Expanded modes and is multiplexed with the LSTRB function. This pin is not available in the 48 / 52 pin package versions.
2.3.13 PE2 / R/W -- Port E I/O Pin [2] / Read/Write
In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of reset. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR register. External writes will not be possible until enabled. This pin is not available in the 48 / 52 pin package versions.
2.3.14 PE1 / IRQ -- Port E input Pin [1] / Maskable Interrupt Pin
The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). IRQ is always enabled and configured to level-sensitive triggering out of reset. It can be disabled by clearing IRQEN bit (INTCR register). When the MCU is reset the IRQ function is masked in the condition code register. This pin is always an input and can always be read. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register.
2.3.15 PE0 / XIRQ -- Port E input Pin [0] / Non Maskable Interrupt Pin
The XIRQ input provides a means of requesting a non maskable interrupt after reset initialization. During reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU software enables it. Because the XIRQ input is level sensitive, it can be connected to a multiple-source wired-OR network. This pin is always an input and can always be read. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register.
2.3.16 PAD[7:0] / AN[7:0] -- Port AD I/O Pins [7:0]
PAD7-PAD0 are general purpose I/O pins and also analog inputs for the analog to digital converter. In order to use a PAD pin as a standard I/O, the corresponding ATDDIEN register bit must be set. These bits are cleared out of reset to configure the PAD pins for A/D operation. When the A/D converter is active in multi-channel mode, port inputs are scanned and converted irrespective of PortAD configuration. Thus PortAD pins that are configured as digital inputs or digital outputs are also converted in the A/D conversion sequence.
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2.3.17 PP[7] / KWP[7] -- Port P I/O Pin [7]
PP7 is a general purpose input or output pin, shared with the keypad interrupt function. When configured as an input, it can generate interrupts causing the MCU to exit STOP or WAIT mode. This pin is not available in the 48 / 52 pin package versions.
2.3.18 PP[6] / KWP[6]/ROMCTL -- Port P I/O Pin [6]
PP6 is a general purpose input or output pin, shared with the keypad interrupt function. When configured as an input, it can generate interrupts causing the MCU to exit STOP or WAIT mode. This pin is not available in the 48 / 52 pin package versions. During MCU expanded modes of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. PP6=1 in emulation modes equates to ROMON =0 (ROM space externally mapped) PP6=0 in expanded modes equates to ROMON =0 (ROM space externally mapped)
2.3.19 PP[5:0] / KWP[5:0] / PW[5:0] -- Port P I/O Pins [5:0]
PP[5:0] are general purpose input or output pins, shared with the keypad interrupt function. When configured as inputs, they can generate interrupts causing the MCU to exit STOP or WAIT mode. PP[5:0] are also shared with the PWM output signals, PW[5:0]. Pins PP[2:0] are only available in the 80 pin package version. Pins PP[4:3] are not available in the 48 pin package version.
2.3.20 PJ[7:6] / KWJ[7:6] -- Port J I/O Pins [7:6]
PJ[7:6] are general purpose input or output pins, shared with the keypad interrupt function. When configured as inputs, they can generate interrupts causing the MCU to exit STOP or WAIT mode. These pins are not available in the 48 pin package version nor in the 52 pin package version.
2.3.21 PM5 / SCK -- Port M I/O Pin 5
PM5 is a general purpose input or output pin and also the serial clock pin SCK for the Serial Peripheral Interface (SPI).
2.3.22 PM4 / MOSI -- Port M I/O Pin 4
PM4 is a general purpose input or output pin and also the master output (during master mode) or slave input (during slave mode) pin for the Serial Peripheral Interface (SPI).
2.3.23 PM3 / SS -- Port M I/O Pin 3
PM3 is a general purpose input or output pin and also the slave select pin SS for the Serial Peripheral Interface (SPI).
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2.3.24 PM2 / MISO -- Port M I/O Pin 2
PM2 is a general purpose input or output pin and also the master input (during master mode) or slave output (during slave mode) pin for the Serial Peripheral Interface (SPI).
2.3.25 PM1 / TXCAN -- Port M I/O Pin 1
PM1 is a general purpose input or output pin and the transmit pin, TXCAN, of the CAN module.
2.3.26 PM0 / RXCAN -- Port M I/O Pin 0
PM0 is a general purpose input or output pin and the receive pin, RXCAN, of the CAN module.
2.3.27 PS[3:2] -- Port S I/O Pins [3:2]
PS3 and PS2 are general purpose input or output pins. These pins are not available in the 48 / 52 pin package versions.
2.3.28 PS1 / TXD -- Port S I/O Pin 1
PS1 is a general purpose input or output pin and the transmit pin, TXD, of Serial Communication Interface (SCI).
2.3.29 PS0 / RXD -- Port S I/O Pin 0
PS0 is a general purpose input or output pin and the receive pin, RXD, of Serial Communication Interface (SCI).
2.3.30 PPT[7:5] / IOC[7:5] -- Port T I/O Pins [7:5]
PT7-PT5 are general purpose input or output pins. They can also be configured as the timer system input capture or output compare pins IOC7-IOC5.
2.3.31 PT[4:0] / IOC[4:0] / PW[4:0]-- Port T I/O Pins [4:0]
PT4-PT0 are general purpose input or output pins. They can also be configured as the timer system input capture or output compare pins IOC4-IOC0 or as the PWM outputs PW[4:0].
2.4 Power Supply Pins
2.4.1 VDDX,VSSX -- Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are loaded.
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2.4.2 VDDR, VSSR -- Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
External power and ground for the internal voltage regulator. Connecting VDDR to ground disables the internal voltage regulator.
2.4.3 VDD1, VDD2, VSS1, VSS2 -- Internal Logic Power Pins
Power is supplied to the MCU through VDD and VSS. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VDDR is tied to ground.
2.4.4 VDDA, VSSA -- Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator reference and the analog to digital converter.
2.4.5 VRH, VRL -- ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL -- Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by the internal voltage regulator.
Table 2-2 MC9S12C-Family Power and Ground Connection Summary
Mnemonic
VDD1 VDD2 VSS1 VSS2 VDDR VSSR VDDX VSSX VDDA VSSA VRH VRL
Nominal Voltage
2.5 V 0V 5.0 V 0V 5.0 V 0V 5.0 V 0V 5.0 V 0V
Description
Internal power and ground generated by internal regulator.. These also allow an external source to supply the core VDD/VSS voltages and bypass the internal voltage regulator. In the 48 and 52 LQFP packages VDD2 and VSS2 are not available. External power and ground, supply to internal voltage regulator.
External power and ground, supply to pin drivers. Operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently. Reference voltage low for the ATD converter.. In the 48 and 52 LQFP packages VRL is bonded to VSSA.
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01 Nominal Voltage
2.5 V 0V
Mnemonic
VDDPLL VSSPLL
Description
Provides operating voltage and ground for the Phased-Locked Loop.. This allows the supply voltage to the PLL to be bypassed independently.. Internal power and ground generated by internal regulator.
NOTE:All VSS pins must be connected together in the application. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on MCU pin load.
Section 3 System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for details on clock generation.
S12_CORE core clock
Flash RAM TIM ATD EXTAL PIM SCI CRG bus clock oscillator clock XTAL VREG TPM SPI MSCAN
Figure 3-1 Clock Connections
Section 4 Modes of Operation
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4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12C Family. Each mode has an associated default memory map and external bus configuration controlled by a further pin. Three low power modes exist for the device.
4.2 Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset. The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal. Table 4-1 Mode Selection
BKGD = MODC
0
PE6 = MODB
0
PE5 = MODA
0
PP6 = ROMCTL
X 0 1 X 0 1 X 0 1 X 0 1
ROMON Bit
1 1 0 0 1 0 1 0 1 1 0 1
Mode Description
Special Single Chip, BDM allowed and ACTIVE.. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed Special Test (Expanded Wide), BDM allowed Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Peripheral; BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide, BDM allowed
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
For further explanation on the modes refer to the S12_MEBI block guide.
Table 4-2 Clock Selection Based on PE7
PE7 = XCLKS
1 0
Description
Colpitts Oscillator selected Pierce Oscillator/external clock selected
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4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: * * * Protection of the contents of FLASH, Operation in single-chip mode, Operation from external memory with internal FLASH disabled.
The user must be reminded that part of the security must lie with the user's code. An extreme example would be user's code that dumps the contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a back door in the user's program. An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH, the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. The security byte resides in a portion of the Flash array. Check the Flash Block User Guide for more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked. 4.3.2.2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH will be disabled. BDM operations will be blocked.
4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH must be erased. This can be done through an external program in expanded mode or via a sequence of BDM commands. Unsecuring is also possible via the Backdoor Key Access. Refer to Flash Block Guide for details. Once the user has erased the FLASH, the part can be reset into special single chip mode. This invokes a program that verifies the erasure of the internal FLASH. Once this program completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but
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the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again.
4.4 Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block User Guide for information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of information about the clock system is the Clock and Reset Generator User Guide (CRG).
4.4.1 Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode. Wake up from this mode can be done via reset or external interrupts.
4.4.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are turned off. This mode consumes more current than the full STOP mode, but the wake up time from this mode is significantly shorter.
4.4.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active. For further power consumption reduction the peripherals can individually turn off their local clocks.
4.4.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power.
Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information .
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5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority. Table 5-1 Interrupt Vector Locations
Vector Address
$FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB $FFF8, $FFF9 $FFF6, $FFF7 $FFF4, $FFF5 $FFF2, $FFF3 $FFF0, $FFF1 $FFEE, $FFEF $FFEC, $FFED $FFEA, $FFEB $FFE8, $FFE9 $FFE6, $FFE7 $FFE4, $FFE5 $FFE2, $FFE3 $FFE0, $FFE1 $FFDE, $FFDF $FFDC, $FFDD $FFDA, $FFDB $FFD8, $FFD9 $FFD6, $FFD7 $FFD4, $FFD5 $FFD2, $FFD3 $FFD0, $FFD1 $FFCE, $FFCF $FFCC, $FFCD $FFCA, $FFCB $FFC8, $FFC9 $FFC6, $FFC7 $FFC4, $FFC5 $FFBA to $FFC3 $FFB8, $FFB9 $FFB6, $FFB7 $FFB4, $FFB5 $FFB2, $FFB3 FLASH CAN wake-up CAN errors CAN receive CRG PLL lock CRG Self Clock Mode Port J ATD
Interrupt Source
External Reset, Power On Reset or Low Voltage Reset (see CRG Flags Register to determine reset source) Clock Monitor fail reset COP failure reset Unimplemented instruction trap SWI XIRQ IRQ Real Time Interrupt Standard Timer channel 0 Standard Timer channel 1 Standard Timer channel 2 Standard Timer channel 3 Standard Timer channel 4 Standard Timer channel 5 Standard Timer channel 6 Standard Timer channel 7 Standard Timer overflow Pulse accumulator A overflow Pulse accumulator input edge SPI SCI
CCR Mask
None None None None None X-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Reserved I-Bit Reserved I-Bit Reserved Reserved Reserved I-Bit I-Bit Reserved I-Bit I-Bit I-Bit I-Bit
Local Enable
None COPCTL (CME, FCME) COP rate select None None None INTCR (IRQEN) CRGINT (RTIE) TIE (C0I) TIE (C1I) TIE (C2I) TIE (C3I) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TMSK2 (TOI) PACTL (PAOVI) PACTL (PAI) SPICR1 (SPIE, SPTIE) SCICR2 (TIE, TCIE, RIE, ILIE) ATDCTL2 (ASCIE) PIEP (PIEP7-6)
HPRIO Value to Elevate
- - - - - - $F2 $F0 $EE $EC $EA $E8 $E6 $E4 $E2 $E0 $DE $DC $DA $D8 $D6
$D2 $CE
PLLCR (LOCKIE) PLLCR (SCMIE) FCNFG (CCIE, CBEIE) CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE)
$C6 $C4 $B8 $B6 $B4 $B2
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$FFB0, $FFB1 $FF90 to $FFAF $FF8E, $FF8F $FF8C, $FF8D $FF8A, $FF8B $FF80 to $FF89 Port P PWM Emergency Shutdown VREG LVI CAN transmit I-Bit I-Bit I-Bit I-Bit Reserved CANTIER (TXEIE[2:0]) PIEP (PIEP7-0) PWMSDN(PWMIE) CTRL0 (LVIE) $B0 $8E $8C $8A
Reserved
5.3 Resets
Resets are a subset of the interrupts featured inTable 5-1. The different sources capable of generating a system reset are summarized in Table 5-2. When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block User Guides for register reset states.
5.3.1 Reset Summary Table
Table 5-2 Reset Summary
Reset
Power-on Reset External Reset Low Voltage Reset Clock Monitor Reset COP Watchdog Reset
Priority
1 1 1 2 3
Source
CRG Module RESET pin VREG Module CRG Module CRG Module
Vector
$FFFE, $FFFF $FFFE, $FFFF $FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB
5.3.2 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block User Guides for register reset states. Refer to the HCS12 Multiplexed External Bus Interface (MEBI) Block Guide for mode dependent pin configuration of port A, B and E out of reset. Refer to the PIM Block User Guide for reset configurations of all peripheral module ports. Refer to Figure 1-2 to Figure 1-5 footnotes for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset.
NOTE:
For devices assembled in 48-pin or 52-pin LQFP packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 2-1 for affected pins.
Section 6 HCS12 Core Block Description
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Consult the individual block guides for information about the HCS12 core modules, i.e. central processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed external bus interface (MEBI), debug12 module (DBG12) and background debug mode module (BDM). Where the CPU12 Reference Manual refers to cycles this is equivalent to device bus clock periods.
6.1 Device-specific information
6.1.1 PPAGE
External paging is not supported on these devices. In order to access the 16K flash blocks in the address range $8000-$BFFF the PPAGE register must be loaded with the corresponding value for this range. Refer to Table 6-1 for device specific page mapping. For all devices Flash Page 3F is visible in the $C000-$FFFF range if ROMON is set. For all devices Page 3E is also visible in the $4000-$7FFF range if ROMHM is cleared and ROMON is set. For all devices apart from MC9S12C32 Flash Page 3D is visible in the $0000-$3FFF range if ROMON is set... Table 6-1 Device Specfic Flash PAGE Mapping
Device
MC9S12C32 MC9S12C32 MC9S12C64 MC9S12C64 MC9S12C64 MC9S12C64 MC9S12C96 MC9S12C96 MC9S12C96 MC9S12C96 MC9S12C96 MC9S12C96 MC9S12C128 MC9S12C128 MC9S12C128 MC9S12C128 MC9S12C128 MC9S12C128 MC9S12C128 MC9S12C128
PAGE
3E 3F 3C 3D 3E 3F 3A 3B 3C 3D 3E 3F 38 39 3A 3B 3C 3D 3E 3F
PAGE visible with PPAGE contents
$00,$02,$04,$06,$08,$0A,$0C,$0E,$10,$12......$2C,$2E,$30,$32,$34,$36,$38,$3A,$3C,$3E $01,$03,$05,$07,$09,$0B,$0D,$0F,$11,$13.....$2D,$2F,$31,$33,$35,$37,$39,$3B,$3D,$3F $00,$04,$08,$0C,$10,$14,$18,$1C,$20,$24,$28,$2C,$30,$34,$38,$3C $01,$05,$09,$0D,$11,$15,$19,$1D,$21,$25,$29,$2D,$31,$35,$39,$3D $02,$06,$0A,$0E,$12,$16,$1A,$1E,$22,$26,$2A,$2E,$32,$36,$3A,$3E $03,$07,$0B,$0F,$13,$17,$1B,$1F,$23,$27,$2B,$2F,$33,$37,$3B,$3F $00,$02,$08,$0A,$10,$12,$18,$1A,$20,$22,$28,$2A,$30,$32,$38,$3A $01,$03,$09,$0B,$11,$13,$19,$1B,$21,$23,$29,$2B,$31,$33,$39,$3B $04,$0C,$14,$1C,$24,$2C,$34,$3C $05,$0D,$15,$1D,$25,$2D,$35,$3D $06,$0E,$16,$1E,$26,$2E,$36,$3E $07,$0F,$17,$1F,$27,$2F,$37,$3F $00,$08,$10,$18,$20,$28,$30,$38 $01,$09,$11,$19,$21,$29,$31,$39 $02,$0A,$12,$1A,$22,$2A,$32,$3A $03,$0B,$13,$1B,$23,$2B,$33,$3B $04,$0C,$14,$1C,$24,$2C,$34,$3C $05,$0D,$15,$1D,$25,$2D,$35,$3D $06,$0E,$16,$1E,$26,$2E,$36,$3E $07,$0F,$17,$1F,$27,$2F,$37,$3F
6.1.2 BDM alternate clock
The BDM section of S12 Core User Guide reference to alternate clock is equivalent to oscillator clock.
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6.1.3 Extended Address Range Emulation Implications
In order to emulate the MC9S12C-Family devices, external addressing of a 128K memory map is required. This is provided in a 112 LQFP package version which includes the 3 necessary extra external address bus signals via PortK[2:0]. This package version is for emulation only and not provided as a general production package. The reset state of DDRK in the S12_CORE is $00, configuring the pins as inputs. The reset state of PUPKE in the PUCR register of the S12_CORE is "1" enabling the internal PortK pullups. In this reset state the pull-ups provide a defined state and prevent a floating input, thereby preventing unneccesary current flow at the input stage. To prevent unneccesary current flow in production package options, the states of DDRK and PUPKE should not be changed by software.
Section 7 Voltage Regulator (VREG) Block Description
Consult the VREG Block User Guide for information about the dual output linear voltage regulator.
7.1 Device-specific information
The VREG is part of the IPBus domain.
7.1.1 VREGEN
VREGEN is connected internally to VDDR.
7.1.2 VDD1, VDD2, VSS1, VSS2
In the 80 pin QFP package versions, both internal VDD and VSS of the 2.5V domain are bonded out on 2 sides of the device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1 and VDD2 are connected together internally. VSS1 and VSS2 are connected together internally. The extra pin pair enables systems using the 80 pin package to employ better supply routing and further decoupling.
Section 8 Recommended Printed Circuit Board Layout
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed:
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* * * * * * *
Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (C1 - C6). Central point of the ground star should be the VSSR pin. Use low ohmic low inductance connections between VSS1, VSS2 and VSSR. VSSPLL must be directly connected to VSSR. Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7, C8, C11 and Q1 as small as possible. Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the connection area to the MCU. Central power input should be fed in at the VDDA/VSSA pins.
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Table 8-1 Recommended External Component Values
Component
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 R1 R2 / RB R3 / RS Q1
Purpose
VDD1 filter cap VDD2 filter cap (80 QFP only) VDDA filter cap VDDR filter cap VDDPLL filter cap VDDX filter cap OSC load cap
Type
ceramic X7R ceramic X7R ceramic X7R X7R/tantalum ceramic X7R X7R/tantalum
Value
220nF, 470nF1 220nF 100nF >=100nF 100nF >=100nF
See PLL specification chapter OSC load cap PLL loop filter cap See PLL specification chapter PLL loop filter cap DC cutoff cap PLL loop filter res PLL loop filter res Pierce mode only PLL loop filter res Quartz Colpitts mode only, if recommended by quartz manufacturer See PLL Specification chapter
NOTES: 1. In 48LQFP and 52LQFP package versions, VDD2 is not available.. Thus 470nF must be connected to VDD1.
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Figure 8-1 Recommended PCB Layout (48 LQFP)
VDDX
C6 VSSX
VSSA
C3
VDDA VDD1 C1 VSS1
VSSR C4 C5
VDDR
C8
C7
C11
Note : Oscillator in Colpitts mode.
Q1 VSSPLL VDDPLL
C9 R1
C10
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Figure 8-2 Recommended PCB Layout (52 LQFP)
NOTE : Oscillator in Colpitts mode.
VDDX
C6 VSSX VSSA
C3
VDDA VDD1 C1 VSS1
VSSR C4 C5 VDDR C8 Q1 VSSPLL VDDPLL C7 C11 C9 R1 C10
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Figure 8-3 Recommended PCB Layout (80 QFP)
NOTE : Oscillator in Colpitts mode.
VSSA
C3
VSSX
VDDX
C6
VDDA
VDD1 C1 VSS1
VSS2
C2 VDD2
VSSR
C4 C5
VDDR
C8
Q1
C7
C11
C9
R1
C10
VSSPLL VDDPLL
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Figure 8-4 Recommended PCB Layout for 48 LQFP Pierce Oscillator
VDDX
C6 VSSX
VSSA
C3
VDDA VDD1 C1 VSS1
VSSR C4
R3
VDDR
C5
C8
R2 Q1
C7
C10
R1
C9
VSSPLL VDDPLL
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Figure 8-5 Recommended PCB Layout for 52 LQFP Pierce Oscillator
VDDX
C6 VSSX VSSA
C3
VDDA VDD1 C1 VSS1
VSSR C4 VDDR
Q1
R3
C5
C8
R2
C7
C10
R1
C9
VSSPLL VDDPLL
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Figure 8-6 Recommended PCB Layout for 80QFP Pierce Oscillator
VDDX
C6
VSSX
VSSA
C3
VDDA
VDD1 VSS2
C1 C2
VSS1 VDD2
VSSPLL
VSSR C4 C5 VDDR
R2 Q1 C8 C7 R3
C10
R1
Section 9 Clock Reset Generator (CRG) Block Description
Consult the CRG Block User Guide for information about the Clock and Reset Generator module.
9.1 Device-specific information
The CRG is part of the IPBus domain.
C9
VSSPLL VDDPLL
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The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the VREG Block User Guide for voltage level specifications.
9.1.1 XCLKS
The XCLKS input signal is active low (see 2.3.8 PE7 / NOACC / XCLKS -- Port E I/O Pin 7).
Section 10 Oscillator (OSC) Block Description
Consult the OSC Block User Guide for information about the Oscillator module.
Section 11 Timer (TIM) Block Description
Consult the TIM_16B8C Block User Guide for information about the Timer module. The TIM is part of the IPBus domain.
Section 12 Analog to Digital Converter (ATD) Block Description
12.1 Device-specific information
The ATD is part of the IPBus domain.
12.1.1 VRL (voltage reference low)
In the 48 and 52 pin package versions, the VRL pad is bonded internally to the VSSA pin. Consult the ATD_10B8C Block User Guide for further information about the A/D Converter module.
Section 13 Serial Communications Interface (SCI) Block Description
Consult the SCI Block User Guide for information about the Serial Communications Interface module. The SCI is part of the IPBus domain.
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Section 14 Serial Peripheral Interface (SPI) Block Description
Consult the SPI Block User Guide for information about the Serial Peripheral Interface module. The SPI is part of the IPBus domain.
Section 15 Flash Block Description
Consult the FTS32K Block User Guide for information about the Flash module for the MC9S12C32. Consult the FTS64K Block User Guide for information about the Flash module for the MC9S12C64. Consult the FTS96K Block User Guidefor information about the Flash module for the MC9S12C96. Consult the FTS128K Block User Guide for information about the Flash module for the MC9S12C128. The Flash is part of the HCS12 Bus domain.
Section 16 RAM Block Description
This module supports single-cycle misaligned word accesses without wait states. The MC9S12C32 features a single 2K byte RAM module. The MC9S12C64, MC9S12C96 and MC9S12C128 versions feature 2 separate 2K byte RAM modules. Consult the SRAM2K Block User Guide for information about the RAM Module The RAM is part of the HCS12 Bus domain.
Section 17 Pulse Width Modulator (PWM) Block Description
Only channels [5:0] of the PWM are implemented on the MC9S12C-Family. Consult the PWM_8B6C Block User Guide for information about the Pulse Width Modulator Module. The PWM is part of the IPBus domain.
Section 18 MSCAN Block Description
Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module.
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The MSCAN is part of the IPBus domain.
Section 19 Port Integration Module (PIM) Block Description
Consult the PIM_9C32 Block User Guide for information about the Port Integration Module for all versions of the MC9S12C-Family. The PIM is part of the IPBus domain. The MODRR register within the PIM allows for mapping of PWM channels to PortT in the absence of PortP pins for the low pin count packages. For the 80QFP package option it is recommended not to use MODRR since this is intended to support PWM channel availability in low pin count packages. Note that when mapping PWM channels to PortT in an 80QFP option, the associated PWM channels are then mapped to both PortP and PortT.
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Appendix A Electrical Characteristics
A.1 General
NOTE:
The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Motorola and are subject to change without notice. The parts are specified and tested over the 5V and 3.3V ranges. For the intermediate range, generally the electrical specifications for the 3.3V range apply, but the parts are not tested in production test in the intermediate range.
NOTE:
This supplement contains the most accurate electrical information for the MC9S12C-Family microcontrollers available at the time of publication. The information should be considered PRELIMINARY and is subject to change. This introduction is intended to give an overview on several common topics like power supply, current injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate.
NOTE:
This classification will be added at a later release of the specification
P: Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. They are regularly verified by production monitors. T: Those parameters are achieved by design characterization on a small sample size from typical devices. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12C-Family utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL as well as the internal logic. The VDDA, VSSA pair supplies the A/D converter. The VDDX, VSSX pair supplies the I/O pins The VDDR, VSSR pair supplies the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic. VDDPLL, VSSPLL supply the oscillator and the PLL.
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VSS1 and VSS2 are internally connected by metal. VDD1 and VDD2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection.
NOTE:
In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins. A.1.3.1 5V I/O pins Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD pin and the RESET inputs.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. pull-up and pull-down resistors may be disabled permanently. A.1.3.2 Analog Reference This class is made up by the two VRH and VRL pins. In 48 and 52 pin package versions the VRL pad is bonded to the VSSA pin. A.1.3.3 Oscillator The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL. A.1.3.4 TEST This pin is used for production testing only.
A.1.4 Current Injection
Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation. Insure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption.
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A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Table A-1 Absolute Maximum Ratings
Num
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Rating
I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage1 PLL Supply Voltage (1) Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single pin limit for all digital I/O pins 2 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL3 Instantaneous Maximum Current Single pin limit for TEST4 Operating Temperature Range (packaged) Operating Temperature Range (junction) Storage Temperature Range
Symbol
VDD5 VDD VDDPLL VDDX VSSX VIN VRH, VRL VILV VTEST I
D
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -25 -25 -0.25 - 40 - 40 - 65
Max
6.5 3.0 3.0 0.3 0.3 6.5 6.5 3.0 10.0 +25 +25 0 125 140 155
Unit
V V V V V V V V V mA mA mA C C C
IDL IDT T
A
TJ Tstg
NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 2. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 3. These pins are internally clamped to VSSPLL and VDDPLL 4. This pin is clamped low to VSSX, but not clamped high. This pin must be tied low in applications.
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A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2 ESD and Latch-up Test Conditions
Model
Series Resistance Storage Capacitance Human Body Number of Pulse per pin positive negative Series Resistance Storage Capacitance Machine Number of Pulse per pin positive negative Minimum input voltage limit Latch-up Maximum input voltage limit 7.5 V
Description
Symbol
R1 C R1 C -
Value
1500 100 3 3 0 200 3 3 -2.5
Unit
Ohm pF
Ohm pF
V
Table A-3 ESD and Latch-Up Protection Characteristics
Num
1 2 3 4
C
C C C C
Rating
Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) Latch-up Current at 125C positive negative Latch-up Current at 27C positive negative
Symbol
VHBM VMM VCDM ILAT
Min
2000 200 500 +100 -100 +200 -200
Max
-
Unit
V V V mA
5
C
ILAT
-
mA
A.1.7 Operating Conditions
This chapter describes the operating conditions of the devices. Unless otherwise noted those conditions apply to all the following data.
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NOTE:
Instead of specifying ambient temperature all parameters are specified for the more meaningful silicon junction temperature. For power dissipation calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics. Table A-4 Operating Conditions
Rating Symbol
VDD5 VDD VDDPLL VDDX VSSX fosc fbus2 T
J
Min
2.97 2.25 2.25 -0.1 -0.1 0.5 0.25 -40
Typ
5 2.5 2.5 0 0 -
Max
5.5 2.75 2.75 0.1 0.1 16 25 140
Unit
V V V V V MHz MHz C
I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage1 PLL Supply Voltage (1) Voltage Difference VDDX to VDDA Voltage Difference VSSX to VSSR and VSSA Oscillator Bus Frequency Operating Junction Temperature Range
NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. . 2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper operation.
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in C can be obtained from: T J = T A + ( P D * JA ) T J = Junction Temperature, [C ] T A = Ambient Temperature, [C ] P D = Total Chip Power Dissipation, [W] JA = Package Thermal Resistance, [C/W] The total power dissipation can be calculated from: P D = P INT + P IO P INT = Chip Internal Power Dissipation, [W]
Two cases with internal voltage regulator enabled and disabled must be considered:
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1. Internal Voltage Regulator disabled P INT = I DD V DD + I DDPLL V DDPLL + I DDA V DDA 2 P IO = R DSON I IO i i
Which is the sum of all output currents on I/O ports associated with VDDX and VDDM. For RDSON is valid: V OL R DSON = ----------- ;for outputs driven low I OL
V DD5 - V OH R DSON = ----------------------------------- ;for outputs driven high I OH 2. Internal voltage regulator enabled P INT = I DDR V DDR + I DDA V DDA IDDR is the current shown in Table A-8 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. 2 P IO = R DSON I IO i i
respectively
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Which is the sum of all output currents on I/O ports associated with VDDX and VDDR. Table A-5 Thermal Package Characteristics1
Num
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
T T T T T T T T T T T T T T T
Rating
Thermal Resistance LQFP48, single layer PCB2 Thermal Resistance LQFP48, double sided PCB with 2 internal planes3 Junction to Board LQFP48 Junction to Case LQFP48 Junction to Package Top LQFP48 Thermal Resistance LQFP52, single sided PCB Thermal Resistance LQFP52, double sided PCB with 2 internal planes Junction to Board LQFP52 Junction to Case LQFP52 Junction to Package Top LQFP52 Thermal Resistance QFP 80, single sided PCB Thermal Resistance QFP 80, double sided PCB with 2 internal planes Junction to Board QFP80 Junction to Case QFP80 Junction to Package Top QFP80
Symbol
JA JA JB JC JT JA JA JB JC JT JA JA JB JC JT
Min
-
Typ
-
Max
69 53 30 20 4
Unit
o
C/W C/W
o
oC/W o o o o
C/W C/W C/W C/W
-
-
65 49 31 17 3
oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W
-
-
52 42 28 18 4
NOTES: 1. The values for thermal resistance are achieved by package simulations 2. PC Board according to EIA/JEDEC Standard 51-2 3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances.
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Table A-6 5V I/O Characteristics
Conditions are 4.5< VDDX <5.5V Termperature from -40C to +140C, unless otherwise noted
Num
1
C
P T Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Input Hysteresis
Rating
Symbol
V
IH
Min
0.65*VDD5 VSS5 - 0.3
Typ
250
Max
VDD5 + 0.3 0.35*VDD5 -
Unit
V V V V mV A
VIH VIL VIL V
HYS
2
P T
3
C
4
P
Input Leakage Current (pins in high ohmic input mode)1 Vin = VDD5 or VSS5 Output High Voltage (pins in output mode) Partial Drive IOH = -2mA Output High Voltage (pins in output mode) Full Drive IOH = -10mA Output Low Voltage (pins in output mode) Partial Drive IOL = +2mA Output Low Voltage (pins in output mode) Full Drive IOL = +10mA Internal Pull Up Device Current, tested at V Max.
IL
I
in
-1
-
1
5 6 7 8
C P C P
V
OH
VDD5 - 0.8 VDD5 - 0.8 -
-
0.8 0.8
V V V V A A A A pF mA s s
VOH VOL V
OL
9
P
IPUL IPUH IPDH IPDL Cin IICS IICP tPIGN tPVAL
-
-
-130
10
C
Internal Pull Up Device Current, tested at V Min.
IH
-10
-
-
11
P
Internal Pull Down Device Current, tested at V Min.
IH
-
-
130
12 13 14
C D T
Internal Pull Down Device Current, tested at V Max.
IL
10
7
2.5 25 3
Input Capacitance Injection current2 Single Pin limit Total Device Limit. Sum of all injected currents Port P, J Interrupt Input Pulse filtered3 Port P, J Interrupt Input Pulse passed3
-2.5 -25
-
15 16
P P
10
NOTES: 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temperature range from 50 C to 125 C. 2. Refer to Section A.1.4 Current Injection, for more details 3. Parameter only applies in STOP or Pseudo STOP mode.
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Table A-7 3.3V I/O Characteristics
Conditions are VDDX=3.3V +/-10%, Termperature from -40C to +140C, unless otherwise noted
Num
1
C
P T Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Input Hysteresis
Rating
Symbol
V
IH
Min
0.65*VDD5 VSS5 - 0.3
Typ
250
Max
VDD5 + 0.3 0.35*VDD5 -
Unit
V V V V mV A
VIH VIL VIL V
HYS
2
P T
3
C
4
P
Input Leakage Current (pins in high ohmic input mode)1 Vin = VDD5 or VSS5 Output High Voltage (pins in output mode) Partial Drive IOH = -0.75mA Output High Voltage (pins in output mode) Full Drive IOH = -4mA Output Low Voltage (pins in output mode) Partial Drive IOL = +0.9mA Output Low Voltage (pins in output mode) Full Drive IOL = +4.75mA Internal Pull Up Device Current, tested at V Max.
IL
I
in
-1
-
1
5
C
V
OH
VDD5 - 0.4 VDD5 - 0.4
-
-
V
6
P
V
OH
-
-
V
7
C
V
OL
-
-
0.4
V
8
P
V
OL
-
-
0.4
V A A A A pF mA s s
9
P
IPUL IPUH IPDH IPDL Cin IICS IICP tPIGN tPVAL
-
-
-60
10
C
Internal Pull Up Device Current, tested at VIH Min. Internal Pull Down Device Current, tested at V Min.
IH
-6
-
-
11
P
-
-
60
12 11 12
C D T
Internal Pull Down Device Current, tested at V Max.
IL
6
7
2.5 25 3
Input Capacitance Injection current2 Single Pin limit Total Device Limit. Sum of all injected currents Port P, J Interrupt Input Pulse filtered3 Port P, J Interrupt Input Pulse passed3
-2.5 -25
-
13 14
P P
10
NOTES: 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temperature range from 50 C to 125 C. 2. Refer to Section A.1.4 Current Injection, for more details 3. Parameter only applies in STOP or Pseudo STOP mode.
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A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator. A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take the single chip currents and add the currents due to the external loads.
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Table A-8 Supply Current Characteristics for MC9S12C32
Conditions are shown in Table A-4 with internal regulator enabled unless otherwise noted Num
1
C
P P P C C P C P C P C P C C C C C C P C P C P C P
Rating
Run Supply Current Single Chip Wait Supply current All modules enabled VDDR<4.9V, only RTI enabled(2) VDDR>4.9V, only RTI enabled Pseudo Stop Current (RTI and COP disabled)(2)(3) -40C 27C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C Pseudo Stop Current (RTI and COP enabled)2 3 -40C 27C 85C 105C 125C Stop Current (3) -40C 27C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C
Symbol
IDD5
Min
Typ
Max
35 30 8
Unit
mA
2
IDDW
3.5 2.5 340 360 500 550 590 720 780 1100 540 700 750 880 1300 10 20 100 140 170 300 350 520
mA
450 1450 1900 4500 A
3
IDDPS1
4
IDDPS1
A
80 1000 1400 4000 A
5
IDDS(1)
NOTES: 1. STOP current measured in production test at increased junction temperature, hence for Temp Option "C" the test is carried out at 100C although the Temperature specification is 85C. Similarly for "v" and "M" options the temperature used in test lies 15C above the temperature option specification. 2. PLL off 3. At those low power dissipation levels TJ = TA can be assumed
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Table A-9 Supply Current Characteristics for MC9S12C64,MC9S12C96,MC9S12C128
Conditions are shown in Table A-4 with internal regulator enabled unless otherwise noted Num
1
C
P P P C C P C P C P C P C C C C C C P C P C P C P
Rating
Run Supply Current Single Chip, Wait Supply current All modules enabled VDDR<4.9V, only RTI enabled(2) VDDR>4.9V, only RTI enabled Pseudo Stop Current (RTI and COP disabled)(2)(3) -40C 27C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C Pseudo Stop Current (RTI and COP enabled)2 3 -40C 27C 85C 105C 125C Stop Current (3) -40C 27C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C
Symbol
IDD5
Min
Typ
Max
45 33 8
Unit
mA
2
IDDW
2.5 3.5 190 200 300 400 450 600 650 1000 370 500 590 780 1200 12 25 130 160 200 350 400 600
mA
250 1400 1900 4800 A
6
IDDPS1
4
IDDPS1
A
100 1200 1700 4500 A
5
IDDS(1)
NOTES: 1. STOP current measured in production test at increased junction temperature, hence for Temp Option "C" the test is carried out at 100C although the Temperature specification is 85C. Similarly for "v" and "M" options the temperature used in test lies 15C above the temperature option specification. 2. PLL off 3. At those low power dissipation levels TJ = TA can be assumed
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Appendix B Electrical Specifications
B.1 Voltage Regulator Operating Conditions
Table B-1 Voltage Regulator Electrical Parameters
Nu m
1 2
C
P C
Characteristic
Input Voltages Regulator Current Reduced Power Mode Shutdown Mode Output Voltage Core Full Performance Mode Low Voltage Interrupt1 Assert Level Deassert Level Low Voltage Reset2 Assert Level C32 Assert Level C64, C96, C128 Low Voltage Reset(2) Deassert Level Power-on Reset3 Assert Level Deassert Level
Symbol
VVDDR, A IREG
Min
2.97 -- --
Typical
-- 20 12
Max
5.5 50 40
Unit
V A A V
3
P
VDD
2.35
2.5
2.75
4
P
VLVIA VLVID
4.30 4.42
4.53 4.65
4.77 4.89
V V
5
P
VLVRA
2.25 2.25
2.3 2.35
--
V
6
P
VLVRD
--
--
2.55
V
7
C
VPORA VPORD
0.97 --
-- --
-- 2.05
V V
NOTES: 1. Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to low supply voltage. 2. Monitors VDD, active only in Full Performance Mode. MCU is monitored by the POR in RPM (see Figure B-1) 3. Monitors VDD. Active in all modes.
NOTE:
The electrical characteristics given in this section are preliminary and should be used as a guide only. Values in this section cannot be guaranteed by Motorola and are subject to change without notice.
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B.2 Chip Power-up and LVI/LVR graphical explanation
Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure B-1. Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) V
VLVID VLVIA VDD VDDA
VLVRD VLVRA VPORD
t
LVI
LVI enabled
POR
LVI disabled due to LVR
LVR
B.3 Output Loads
B.3.1 Resistive Loads
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no external DC loads.
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B.3.2 Capacitive Loads
The capacitive loads are specified in Table B-2. Ceramic capacitors with X7R dielectricum are required. Table B-2 Voltage Regulator - Capacitive Loads
Num
1 2
Characteristic
VDD external capacitive load VDDPLL external capacitive load
Symbol
CDDext CDDPLLext
Min
400 90
Typical
440 220
Max
12000 5000
Unit
nF nF
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B.4 ATD Characteristics
This section describes the characteristics of the analog to digital converter. VRL is not available as a separate pin in the 48 and 52 pin versions. In this case the internal VRL pad is bonded to the VSSA pin. The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the ATD accuracy is generally the same as in the 3.3V range but is not tested in this range in production test.
B.4.1 ATD Operating Characteristics In 5V Range
The Table B-3 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table B-3 ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 5V-10% <= VDDA <=5V+10%
Num
1 2 3 4
C
Reference Potential D C D D
Rating
Low High Differential Reference Voltage1 ATD Clock Frequency ATD 10-Bit Conversion Period Clock Cycles2 Conv, Time at 2.0MHz ATD Clock fATDCLK ATD 8-Bit Conversion Period Clock Cycles2 Conv, Time at 2.0MHz ATD Clock fATDCLK Recovery Time (VDDA=5.0 Volts) Reference Supply current
Symbol VRL VRH VRH-VRL fATDCLK NCONV10 TCONV10 NCONV10 TCONV10 tREC IREF
Min VSSA VDDA/2 4.75 0.5 14 7 12 6
Typ
Max VDDA/2 VDDA
Unit V V V MHz Cycles s Cycles s s mA
5.0
5.25 2.0 28 14 26 13 20 0.375
5
D
5 6
D P
NOTES: 1. Full accuracy is not guaranteed when differential voltage is less than 4.75V 2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks.
B.4.2 ATD Operating Characteristics In 3.3V Range
The Table B-3 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive
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beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped
Table B-4 ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= VDDA <= 3.3V+10%
Num C
Reference Potential 1 2 3 4 D
Rating
Low High
Symbol VRL VRH VRH-VRL fATDCLK
Min VSSA VDDA/2 3.0 0.5 14 7 12 6
Typ
Max VDDA/2 VDDA
Unit V V V MHz Cycles s Cycles s s mA
C Differential Reference Voltage D ATD Clock Frequency ATD 10-Bit Conversion Period D
3.3
3.6 2.0 28 14 26 13 20 0.250
Clock Cycles1 NCONV10 Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10 ATD 8-Bit Conversion Period Clock Cycles(1) Conv, Time at 2.0MHz ATD Clock fATDCLK
5
D
NCONV8 TCONV8 tREC IREF
6 7
D Recovery Time (VDDA=3.3 Volts) P Reference Supply current
NOTES: 1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks.
B.4.3 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influenceon the accuracy of the ATD. B.4.3.1 Source Resistance: Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowable. B.4.3.2 Source capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage 1LSB, then the external filter capacitor, Cf 1024 * (CINS- CINN).
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B.4.3.3 Current injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive conditions. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table B-5 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1 2 3 4 5
C
C T C C C
Rating
Max input Source Resistance Total Input Capacitance Non Sampling Sampling Disruptive Analog Input Current Coupling Ratio positive current injection Coupling Ratio negative current injection
Symbol
RS CINN CINS INA Kp Kn
Min
-
Typ
-
Max
1 10 15
Unit
K pF mA A/A A/A
-2.5
2.5 10-4 10-2
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B.4.4 ATD accuracy (5V Range)
Table B-6 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table B-6 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
fATDCLK = 2.0MHz Num
1 2 3 4 5 6 7 8
C
P P P P P P P P 10-Bit Resolution
Rating
Symbol
LSB DNL INL AE LSB DNL INL AE
Min
Typ
5
Max
Unit
mV
10-Bit Differential Nonlinearity 10-Bit Integral Nonlinearity 10-Bit Absolute Error1 8-Bit Resolution 8-Bit Differential Nonlinearity 8-Bit Integral Nonlinearity 8-Bit Absolute Error(1)
-1 -2 -2.5 20 -0.5 -1.0 -1.5 0.5 1
1 2 2.5
Counts Counts Counts mV
0.5 1.0 1.5
Counts Counts Counts
NOTES: 1. These values include quantization error which is inherently 1/2 count for any A/D converter.
B.4.5 ATD accuracy (3.3V Range)
Table B-6 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table B-7 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV
fATDCLK = 2.0MHz Num
1 2 3 4 5 6 7 8
C
P P P P P P P P 10-Bit Resolution
Rating
Symbol
LSB DNL INL AE LSB DNL INL AE
Min
Typ
3.25
Max
Unit
mV
10-Bit Differential Nonlinearity 10-Bit Integral Nonlinearity 10-Bit Absolute 8-Bit Resolution 8-Bit Differential Nonlinearity 8-Bit Integral Nonlinearity 8-Bit Absolute Error(1) Error1
-1.5 -3.5 -5 1.5 2.5 13 -0.5 -1.5 -2.0 1 1.5
1.5 3.5 5
Counts Counts Counts mV
0.5 1.5 2.0
Counts Counts Counts
NOTES: 1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
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For the following definitions see also Figure B-2. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi - Vi - 1 DNL ( i ) = ----------------------- - 1 1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs: n
INL ( n ) =
i=1
Vn - V0 DNL ( i ) = ------------------- - n 1LSB
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DNL
LSB Vi-1
$3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5
10-Bit Absolute Error Boundary Vi 8-Bit Absolute Error Boundary
$FF
$FE
10-Bit Resolution
$3F4 $3F3
$FD
9 8 7 6 5 4 3 2 1 0 3.25 6.5 9.75 13 16.25 19.5 22.75 26 29.25
Ideal Transfer Curve
2
10-Bit Transfer Curve
1
8-Bit Transfer Curve
3286 3289 3292 3295 3299 3302 3305 3309 3312 3315 3318 3321 3324 3328
Vin mV
Figure B-2 ATD Accuracy Definitions
NOTE:
Figure B-2 shows only definitions, for specification values refer to Table B-6.
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B.5 NVM, Flash and EEPROM
B.5.1 NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured. The Flash program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table B-8 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.
B.5.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula.
1 1 t swpgm = 9 --------------------- + 25 ---------f NVMOP f bus
B.5.1.2 Burst Programming This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst programming by keeping the command pipeline filled. The time to program a consecutive word can be calculated as:
1 1 t bwpgm = 4 --------------------- + 9 ---------f NVMOP f bus
The time to program a whole row is:
t brpgm = t swpgm + 31 t bwpgm
Burst programming is more than 2 times faster than single word programming. B.5.1.3 Sector Erase Erasing a 512 byte Flash sector takes:
1 t era 4000 --------------------f NVMOP
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The setup times can be ignored for this operation. B.5.1.4 Mass Erase Erasing a NVM block takes:
1 t mass 20000 --------------------f NVMOP
The setup times can be ignored for this operation.
Table B-8 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1 2 3 4 5 6 7 8 9
C
D D D P D D P P D
Rating
External Oscillator Clock Bus frequency for Programming or Erase Operations Operating Frequency Single Word Programming Time Flash Burst Programming consecutive word Flash Burst Programming Time for 32 Words Sector Erase Time Mass Erase Time Blank Check Time Flash per block
Symbol
fNVMOSC fNVMBUS fNVMOP tswpgm tbwpgm tbrpgm tera tmass t check
Min
0.5 1 150 462 20.42 678.42 204 1004 115
Typ
Max
501
Unit
MHz MHz
200 74.53 313 1035.53 26.73 1333 327786
kHz s s s ms ms tcyc
NOTES: 1. Restrictions for oscillator in crystal mode apply! 2. Minimum Programming times are achieved under maximum NVM operating frequency f NVMOP and maximum bus frequency fbus. 3. Maximum Erase and Programming times are achieved under particular combinations of f NVMOP and bus frequency f bus . Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance. 4. Minimum Erase times are achieved under maximum NVM operating frequency f NVMOP . 5. Minimum time, if first word in the array is not blank 6. Maximum time to complete check on an erased block.
B.5.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase cycling are specified at <2ppm defects over lifetime at the operating conditions noted. A program/erase cycle is specified as two transitions of the cell value from erased programmed erased, 1 0 1.
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NOTE:
All values shown in Table B-9 are target values and subject to further extensive characterization. Table B-9 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1 2
C
C C
Rating
Data Retention at an average junction temperature of TJavg = 85C Flash number of Program/Erase cycles
Symbol
tNVMRET nFLPE
Min
15 10,000
Typ
Max
Unit
Years Cycles
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B.6 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL).
B.6.1 Startup
Table B-10 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide. Table B-10 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1 2 3 4 5 6
C
T T D D D D POR release level POR assert level
Rating
Symbol
VPORR VPORA PWRSTL nRST PWIRQ tWRS
Min
Typ
Max
2.07
Unit
V V tosc
0.97 2 192 20 14 196
Reset input pulse width, minimum input time Startup from Reset Interrupt pulse width, IRQ edge-sensitive mode Wait recovery startup time
nosc ns tcyc
B.6.1.1 POR The release level VPORR and the assert level VPORA are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. B.6.1.2 LVR The release level VLVRR and the assert level VLVRA are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the LVR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. B.6.1.3 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set.
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B.6.1.4 External Reset When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. B.6.1.5 Stop Recovery Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system. B.6.1.6 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector.
B.6.2 Oscillator
The device features an internal Colpitts oscillator. By asserting the XCLKS input during reset this oscillator can be bypassed allowing the input of a square wave. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode in case no proper oscillation is detected. The quality monitor also determines the minimum oscillator start-up
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time tUPOSC. The device features a clock monitor. A time-out is asserted if the frequency of the incoming clock signal is below the Clock Monitor FailureAssert Frequency fCMFA. Table B-11 Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1a 1b 2 3 4 5 6 7 8 9 10 11 12
C
C C P C D P P D D D D D C
Rating
Crystal oscillator range (Colpitts) Crystal oscillator range (Pierce) 1(4) Startup Current Oscillator start-up time (Colpitts) Clock Quality check time-out Clock Monitor Failure Assert Frequency External square wave input frequency 4 External square wave pulse width low External square wave pulse width high External square wave rise time External square wave fall time Input Capacitance (EXTAL, XTAL pins) DC Operating Bias in Colpitts Configuration on EXTAL Pin
Symbol
fOSC fOSC iOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF CIN VDCBIAS
Min
0.5 0.5 100
Typ
Max
16 40
Unit
MHz MHz A
82 0.45 50 0.5 9.5 9.5 100
1003 2.5 200 50
ms s KHz MHz ns ns
1 1 7 1.1
ns ns pF V
NOTES: 1. Depending on the crystal a damping series resistor might be necessary 2. fosc = 4MHz, C = 22pF. 3. Maximum value is for extreme cases using high Q, low frequency crystals 4. XCLKS =0 during reset
B.6.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLLs Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. B.6.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics.
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Cp VDDPLL Cs fosc fref 1 refdv+1 fcmp R Phase K Detector Loop Divider 1 synr+1
XFC Pin
VCO KV fvco
1 2
Figure B-3 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table B-12. The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used for fOSC = 4MHz and a 25MHz bus clock. The VCO Gain at the desired VCO frequency is approximated by: ( f 1 - f vco ) ---------------------K 1 1V ( 60 - 50 ) ----------------------- 100
KV = K1 e
= - 100 e
= -90.48MHz/V
The phase detector relationship is given by:
K = - i ch K V
ich is the current in tracking mode.
= 316.7Hz/
The loop bandwidth fC should be chosen to fulfill the Gardner's stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response.
2 f ref f ref 1 f C < ------------------------------------------ ----- f C < ------------- ;( = 0.9 ) 4 10 10 2 + 1 + fC < 25kHz
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And finally the frequency relationship is defined as
f VCO n = ------------ = 2 ( synr + 1 ) f ref
= 50
With the above values the resistance can be calculated. The example is shown for a loop bandwidth fC=10kHz:
2 n fC R = ---------------------------- = 2**50*10kHz/(316.7Hz/)=9.9k=~10k K
The capacitance Cs can now be calculated as:
0.516 2 C s = --------------------- -------------- ;( = 0.9 ) = 5.19nF =~ 4.7nF fC R fC R
The capacitance Cp should be chosen in the range of:
2
C s 20 C p C s 10
Cp = 470pF
B.6.3.2 Jitter Information The basic functionality of the PLL is shown in Figure B-3. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure B-4.
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0
1
2
3
N-1
N
tmin1 tnom tmax1 tminN tmaxN
Figure B-4 Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as:
t min ( N ) t max ( N ) J ( N ) = max 1 - -------------------- , 1 - -------------------- N t nom N t nom
For N < 100, the following equation is a good fit for the maximum jitter:
j1 J ( N ) = ------- + j 2 N
J(N)
1
5
10
20
N
Figure B-5 Maximum bus clock jitter approximation
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This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent.
Table B-12 PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Rating
Symbol
fSCM fVCO |trk| |Lock| |unl| |unt| tstab tacq tal K1 f1 | ich | | ich | j1 j2
Min
1 8 3 0 0.5 6
Typ
Max
5.5 50 4 1.5 2.5 8
Unit
MHz MHz %1 %(1) %(1) %(1) ms ms ms MHz/V MHz A A
P Self Clock Mode frequency D VCO locking range D Lock Detector transition from Acquisition to Tracking mode
D Lock Detection D Un-Lock Detection D Lock Detector transition from Tracking to Acquisition mode
C PLLON Total Stabilization delay (Auto Mode) 2 D PLLON Acquisition mode stabilization delay (2) D PLLON Tracking mode stabilization delay (2) D Fitting parameter VCO loop gain D Fitting parameter VCO loop frequency D Charge pump current acquisition mode D Charge pump current tracking mode C Jitter fit parameter 1(2) C Jitter fit parameter 2(2)
0.5 0.3 0.2 -100 60 38.5 3.5 1.1 0.13
% %
NOTES: 1. % deviation from target frequency 2. fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs = 10K.
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B.7 MSCAN
Table B-13 MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2
Rating
Symbol
tWUP tWUP
Min
Typ
Max
2
P MSCAN Wake-up dominant pulse filtered P MSCAN Wake-up dominant pulse pass
5
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B.8 SPI
Appendix C Electrical Specifications
This section provides electrical parametrics and ratings for the SPI. In Table C-1 the measurement conditions are listed. Table C-1 Measurement Conditions
Description
Drive mode Load capacitance CLOAD, on all outputs Thresholds for delay measurement points
Value
full drive mode 50 (20% / 80%) VDDX
Unit
-- pF V
C.1 Master Mode
In Figure C-1 the timing diagram for master mode with transmission format CPHA=0 is depicted.
SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 10 MOSI (OUTPUT)
1.if configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1 4 4
12
13
3
12
13
6 MSB IN2 BIT 6 . . . 1 9 MSB OUT2 BIT 6 . . . 1 LSB OUT LSB IN 11
Figure C-1 SPI Master Timing (CPHA=0) In Figure C-2 the timing diagram for master mode with transmission format CPHA=1 is depicted.
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SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA
1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
12
13
3
4
12
13
6 MSB IN2 BIT 6 . . . 1 11 LSB IN
MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
Figure C-2 SPI Master Timing (CPHA=1) In Table C-2 the timing characteristics for master mode are listed. Table C-2 SPI Master Mode Timing Characteristics
Num
1 1 2 3 4 5 6 9 10 11 12 13
C
P P D D D D D D D D D D
Characteristic
SCK Frequency SCK Period Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Data Valid after SCK Edge Data Valid after SS fall (CPHA=0) Data Hold Time (Outputs) Rise and Fall Time Inputs Rise and Fall Time Outputs
Symbol
fsck tsck tlead tlag twsck tsu thi tvsck tvss tho trfi trfo
Min
1/2048 2 -- -- -- 8 8 -- -- 20 -- --
Typ
-- -- 1/2 1/2 1/2 -- -- -- -- -- -- --
Max
1/2 2048 -- -- -- -- -- 30 15 -- 8 8
Unit
fbus tbus tsck tsck tsck ns ns ns ns ns ns ns
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C.2 Slave Mode
In Figure C-3 the timing diagram for slave mode with transmission format CPHA=0 is depicted.
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 10 7 MISO (OUTPUT) see note 5 MOSI (INPUT) NOTE: Not defined! MSB IN SLAVE MSB 6 BIT 6 . . . 1 LSB IN 9 BIT 6 . . . 1 4 4 12 13 8 11 11 SEE NOTE 12 13 3
SLAVE LSB OUT
Figure C-3 SPI Slave Timing (CPHA=0) In Figure C-4 the timing diagram for slave mode with transmission format CPHA=1 is depicted.
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SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) 4 SCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) see note 7 MOSI (INPUT) NOTE: Not defined! SLAVE 5 MSB IN MSB OUT 6 BIT 6 . . . 1 LSB IN 4 12 13 12 13 3
11 BIT 6 . . . 1 SLAVE LSB OUT
8
Figure C-4 SPI Slave Timing (CPHA=1) In Table C-3 the timing characteristics for slave mode are listed. Table C-3 SPI Slave Mode Timing Characteristics
Num
1 1 2 3 4 5 6 7 8 9 10 11 12 13
C
D P D D D D D D D D D D D D
Characteristic
SCK Frequency SCK Period Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Slave Access Time (time to data active) Slave MISO Disable Time Data Valid after SCK Edge Data Valid after SS fall Data Hold Time (Outputs) Rise and Fall Time Inputs Rise and Fall Time Outputs
Symbol
fsck tsck tlead tlag twsck tsu thi ta tdis tvsck tvss tho trfi trfo
Min
DC 4 4 4 4 8 8 -- -- -- -- 20 -- --
Typ
-- -- -- -- -- -- -- -- -- -- -- -- -- --
Max
1/4 -- -- -- -- -- 20 22 30 + tbus
1
Unit
fbus tbus tbus tbus tbus ns ns ns ns ns ns ns ns ns
30 + tbus 1 -- 8 8
NOTES: 1. tbus added due to internal synchronization delay
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C.3 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure C-5 with the actual timing values shown on table Table C-4. All major bus signals are included in the diagram. While both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
C.3.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs. Figure C-5 General External Bus Timing
1, 2 3 ECLK PE4 5 9 Addr/Data (read) PA, PB data 6 15 addr 7 12 Addr/Data (write) PA, PB data addr 8 14 data 13 16 10 data 11 4
17 R/W PE2
18
19
20 LSTRB PE3
21
22
23 NOACC PE7
24
25
26 PIPO0 PIPO1, PE6,5
27
28
29
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Table C-4 Expanded Bus Timing Characteristics (5V Range)
Conditions are 4.75V < VDDX < 5.25V, Junction Temperature -40C to +140C, CLOAD = 50pF
Num
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
C
P P D D D D D D D D D D D D D D D D D D D D D D D D D D D
Rating
Frequency of operation (E-clock) Cycle time Pulse width, E low Pulse width, E high1 Address delay time Address valid time to E rise (PWEL-tAD) Muxed address hold time Address hold to data valid Data hold to address Read data setup time Read data hold time Write data delay time Write data hold time Write data setup time(1) (PWEH-tDDW) Address access time(1) (tcyc-tAD-tDSR) E high access time(1) (PWEH-tDSR) Read/write delay time Read/write valid time to E rise (PWEL-tRWD) Read/write hold time Low strobe delay time Low strobe valid time to E rise (PWEL-tLSD) Low strobe hold time NOACC strobe delay time NOACC valid time to E rise (PWEL-tLSD) NOACC hold time IPIPO[1:0] delay time IPIPO[1:0] valid time to E rise (PWEL-tP0D) IPIPO[1:0] delay time(1) (PWEH-tP1V) IPIPO[1:0] valid time to E fall
Symbol
fo tcyc PWEL PWEH tAD tAV tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV tNOH tP0D tP0V tP1D tP1V
Min
0 40 19 19
Typ
Max
25.0
Unit
MHz ns ns ns
8 11 2 7 2 13 0 7 2 12 19 6 7 14 2 7 14 2 7 14 2 2 11 2 11 25 7
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
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Table C-5 Expanded Bus Timing Characteristics (3.3V Range)
Conditions are VDDX=3.3V+/-10%, Junction Temperature -40C to +140C, CLOAD = 50pF
Num
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
C
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
Rating
Frequency of operation (E-clock) Cycle time Pulse width, E low Pulse width, E high1 Address delay time Address valid time to E rise (PWEL-tAD) Muxed address hold time Address hold to data valid Data hold to address Read data setup time Read data hold time Write data delay time Write data hold time Write data setup time(1) (PWEH-tDDW) Address access time(1) E high access time(1) (PWEH-tDSR) Read/write delay time Read/write valid time to E rise (PWEL-tRWD) Read/write hold time Low strobe delay time Low strobe valid time to E rise (PWEL-tLSD) Low strobe hold time NOACC strobe delay time NOACC valid time to E rise (PWEL-tLSD) NOACC hold time IPIPO[1:0] delay time IPIPO[1:0] valid time to E rise (PWEL-tP0D) IPIPO[1:0] delay time(1) IPIPO[1:0] valid time to E fall
Symbol
fo tcyc PWEL PWEH tAD tAV tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV tNOH tP0D tP0V tP1D tP1V
Min
0 62.5 30 30
Typ
Max
16.0
Unit
MHz ns ns ns
16 16 2 7 2 15 0 15 2 15 29 15 14 16 2 14 16 2 14 16 2 2 16 2 11 25 14
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
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Appendix D Package Information
D.1 General
This section provides the physical dimensions of the MC9S12C Family packages 48LQFP, 52LQFP, 80QFP.
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D.2 80-pin QFP package
L
60 61 41 40
S
S
B B P
D
L
H A-B
B
V 0.05 D
M
M
C A-B
-A-
-B-
S
S
D
0.20
0.20
-A-,-B-,-DDETAIL A
DETAIL A
80 1 20
21
-D0.20
M
F
A H A-B S
S
D
S
0.05 A-B J
S
N
0.20 E C -CSEATING PLANE
M
C A-B
D
S
M DETAIL C -HH G
DATUM PLANE
D 0.20
M
C A-B
S
D
S
SECTION B-B
VIEW ROTATED 90
0.10 M
U T
DATUM PLANE
-H-
R
K W X DETAIL C
Q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V W X
MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC --0.25 0.13 0.23 0.65 0.95 12.35 REF 5 10 0.13 0.17 0.325 BSC 0 7 0.13 0.30 16.95 17.45 0.13 --0 --16.95 17.45 0.35 0.45 1.6 REF
Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B)
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D.3 52-pin LQFP package
4X 4X 13 TIPS
0.20 (0.008) H L-M N
0.20 (0.008) T L-M N -XX=L, M, N
52 1
40 39
C L AB G
3X
VIEW Y -MB V AB VIEW Y F
BASE METAL
-L-
B1
13 14 26 27
V1
PLATING
J D T L-M
U
A1 S1 A S
-N0.13 (0.005)
M
S
N
S
C -H-TSEATING PLANE
4X
2
0.10 (0.004) T
4X
3
VIEW AA
ROTATED 90 CLOCKWISE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003).
SECTION AB-AB
0.05 (0.002)
S
W
1
C2
2X R
R1
0.25 (0.010)
GAGE PLANE
K C1 E VIEW AA Z
DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3
MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0 7 --0 12 REF 12 REF
INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0 7 --0 12 REF 12 REF
Figure D-2 52-pin LQFP Mechanical Dimensions (case no. 848D-03)
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D.4 48-pin LQFP package
4X
0.200 AB T-U Z 9 A1
48 37
A
DETAIL Y
P
1
36
T B B1
12 25
U V AE V1 AE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 1. CONTROLLING DIMENSION: MILLIMETER. 2. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 3. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 7. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 8. EXACT SHAPE OF EACH CORNER IS OPTIONAL. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0 7 12 REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
13
24
Z S1 S
4X
T, U, Z DETAIL Y
0.200 AC T-U Z
AB
G
0.080 AC
AD AC
BASE METAL
DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA
M
TOP & BOTTOM
R
GAUGE PLANE
C F D 0.080
M
E
AC T-U Z H W DETAIL AD AA K L
SECTION AE-AE
Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F)
126
0.250
N
J
Device User Guide -- 9S12C-FamilyDGV1/D V01.01
Appendix E Emulation Information
E.1 General
In order to emulate the MC9S12C-Family devices, external addressing of a 128K memory map is required. This is provided in a 112 LQFP package version which includes the 3 necessary extra external address bus signals via PortK. This package version is for emulation only and not provided as a general production package.
PP4/KWP4/PW4 PP5/KPW5/PWM NC PP7/KWP7/PW7 NC VDDX VSSX PM0/RXCAN PM1/TXCAN PM2/MIS PM3/SS PM4/MOSI PM5/SCK PJ6/KWJ6 PJ7/KWJ7 NC NC PP6/KWP6/ROMONE NC NC PS3 PS2 PS1/TXD PS0/RXD NC NC VSSA VRL PW3/KWP3/PP3 PW2/KWP2/PP2 PW1/KWP1/PP1 /PW0/KWP0/PP0 NC XADDR16/PK2 XADDR15/PK1 XADDR14/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 NC NC NC NC MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
MC9S12C Family
Signals shown in Bold are available only in the 112 Pin Package. Pins marked "NC" are not connected
Figure 19-1 Pin Assignments in 112-pin LQFP
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 NC NC NC NC XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST NC NC NC NC LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
VRH VDDA NC PAD07/AN07 NC PAD06/AN06 NC PAD05/AN05 NC PAD04/AN04 NC PAD03/AN03 NC PAD02/AN02 NC PAD01/AN01 NC PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
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E.1.1 PK[2:0] / XADDR[16:14]
PK2-PK0 provide the expanded address XADDR[16:14] for the external bus. Refer to the S12 Core user guide for detailed information about external address page access.
Pin Name Function 1
PK[2:0]
Pin Name Function 2
XADDR[16:14]
Power Domain
VDDX
Internal Pull Resistor
CTRL PUPKE Reset State Up Port K I/O Pins
Description
The reset state of DDRK in the S12_CORE is $00, configuring the pins as inputs. The reset state of PUPKE in the PUCR register of the S12_CORE is "1" enabling the internal pullup resistors at PortK[2:0]. In this reset state the pull-up resistors provide a defined state and prevent a floating input, thereby preventing unneccesary current consumption at the input stage.
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Device User Guide -- 9S12C-FamilyDGV1/D V01.01
E.2 112-pin LQFP package
4X PIN 1 IDENT 1 112
0.20 T L-M N
4X 28 TIPS 85 84
0.20 T L-M N
J1 J1 C L
4X
P
VIEW Y
108X
G
X X=L, M OR N
VIEW Y B L M B1 V1 V
J
AA
28
57
F D 0.13
M
BASE METAL
29
56
T L-M N
N A1 S1 A S
SECTION J1-J1 ROTATED 90 COUNTERCLOCKWISE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.46. MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 0 7 3 13 11 11 13
C2 C 0.050 2
VIEW AB 0.10 T
112X
SEATING PLANE
3 T
R
R2 0.25
GAGE PLANE
R
R1
C1 (Y) (Z) VIEW AB
(K) E
1
DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3
Figure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanical Dimensions (case no. 841B)
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Device User Guide End Sheet
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